Gate oxide

About: Gate oxide is a research topic. Over the lifetime, 40353 publications have been published within this topic receiving 601517 citations.

ZnO thin film transistor and method of forming the same

Abstract: A zinc oxide (ZnO) thin film transistor (TFT) and method of forming the same are provided. The ZnO may include a ZnO semiconductor channel, a conductive ZnO gate forming an electric field around the ZnO semiconductor channel, an ZnO gate insulator interposed between the conductive ZnO gate and the ZnO semiconductor channel and an insulating ZnO passivation layer on the ZnO semiconductor channel, the conductive ZnO gate and the ZnO gate insulator to protect the ZnO semiconductor channel, the conductive ZnO gate, and the ZnO gate insulator. A thin film transistor (TFT) may be formed by forming a semiconductor channel, forming a conductive gate having an electric field around the semiconductor channel, forming a gate insulator between the conductive gate and the semiconductor channel, and forming an insulating passivation layer on the semiconductor channel, the conductive gate and the gate insulator.

The electronic structure at the atomic scale of ultrathin gate oxides

Abstract: The narrowest feature on present-day integrated circuits is the gate oxide—the thin dielectric layer that forms the basis of field-effect device structures. Silicon dioxide is the dielectric of choice and, if present miniaturization trends continue, the projected oxide thickness by 2012 will be less than one nanometre, or about five silicon atoms across1. At least two of those five atoms will be at the silicon–oxide interfaces, and so will have very different electrical and optical properties from the desired bulk oxide, while constituting a significant fraction of the dielectric layer. Here we use electron-energy-loss spectroscopy in a scanning transmission electron microscope to measure the chemical composition and electronic structure, at the atomic scale, across gate oxides as thin as one nanometre. We are able to resolve the interfacial states that result from the spillover of the silicon conduction-band wavefunctions into the oxide. The spatial extent of these states places a fundamental limit of 0.7 nm (four silicon atoms across) on the thinnest usable silicon dioxide gate dielectric. And for present-day oxide growth techniques, interface roughness will raise this limit to 1.2 nm.

CMOS scaling into the nanometer regime

Abstract: Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping

Abstract: A novel apparatus and method for programming and reading a programmable read only memory (EPROM) having a trapping dielectric layer (20) sandwiched between two silicon dioxide layers (18, 20) is disclosed that greatly reduces the programming time of conventional PROM devices. Examples of the trapping dielectric material are silicon oxide-silicon, nitride-silicon oxide (ONO) and silicon dioxide with buried polysilicon islands. A nonconducting dielectric layer functions as an electrical charge trapping medium. This charging trapping layer is sandwiched between two layers of silicon dioxide acting as an electrical insulator. A conducting gate layer (24) is placed over the upper silicon dioxide layer (22). The memory device (10) is programmed in the conventional manner. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate (24) and the source (14) while the drain is grounded. For the same applied gate voltage, reading in the reverse direction greatly reduces the potential across the trapped charge region.

Low-voltage organic transistors with an amorphous molecular gate dielectric

Abstract: Organic thin film transistors (TFTs) are of interest for a variety of large-area electronic applications, such as displays, sensors and electronic barcodes. One of the key problems with existing organic TFTs is their large operating voltage, which often exceeds 20 V. This is due to poor capacitive coupling through relatively thick gate dielectric layers: these dielectrics are usually either inorganic oxides or nitrides, or insulating polymers, and are often thicker than 100 nm to minimize gate leakage currents. Here we demonstrate a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) gate dielectric and a high-mobility organic semiconductor (pentacene). These TFTs operate with supply voltages of less than 2 V, yet have gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 dielectrics. These results should therefore increase the prospects of using organic TFTs in low-power applications (such as portable devices). Moreover, molecular SAMs may even be of interest for advanced silicon transistors where the continued reduction in dielectric thickness leads to ever greater gate leakage and power dissipation.