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Gate oxide

About: Gate oxide is a research topic. Over the lifetime, 40353 publications have been published within this topic receiving 601517 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, single-wall carbon nanotube field effect transistors (CNFETs) were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) structure, with gate electrodes above the conduction channel separated from the channel by a thin dielectric.
Abstract: We have fabricated single-wall carbon nanotube field-effect transistors (CNFETs) in a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) structure, with gate electrodes above the conduction channel separated from the channel by a thin dielectric These top gate devices exhibit excellent electrical characteristics, including steep subthreshold slope and high transconductance, at gate voltages close to 1 V—a significant improvement relative to previously reported CNFETs which used the substrate as a gate and a thicker gate dielectric Our measured device performance also compares very well to state-of-the-art silicon devices These results are observed for both p- and n-type devices, and they suggest that CNFETs may be competitive with Si MOSFETs for future nanoelectronic applications

785 citations

Proceedings ArticleDOI
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families

729 citations

Journal ArticleDOI
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Abstract: A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

728 citations

Patent
14 Jun 2004
TL;DR: In this article, a zinc oxide polycrystalline (ZnO) semiconductor with a group V element was used for the isolation of the active layer from the atmosphere, where the surface state of the ZnO semiconductor was reduced thanks to the added element.
Abstract: A thin film transistor (1) wherein a gate electrode (3) is formed on an insulative substrate (2), a gate insulating layer (4) is formed on the gate electrode (3), a semiconductor layer (5) is formed on the gate insulating layer (4), a source electrode (6) and a drain electrode (7) are formed on the semiconductor layer (5), and a protective layer (8) covering them are formed. The semiconductor layer (5) is isolated from the atmosphere. The semiconductor layer (5) (active layer) is formed of a ZnO polycrystalline semiconductor doped with, for example, a group V element. Since the surface state of the ZnO semiconductor is reduced thanks to the protective layer (8) and inward expansion of the depletion layer is prevented, the ZnO semiconductor is of an n-type showing its intrinsic resistance value and contains excessive free electrons. The added element acts as acceptor impurities in the ZnO semiconductor, decreasing the excessive electrons. Thus the gate voltage to eliminate the excessive free electrons lowers, thereby making the threshold voltage around 0 V. A semiconductor device using a zinc oxide for an active layer and having a protective layer for isolating the active layer from the atmosphere can be actually used.

715 citations

Journal ArticleDOI
TL;DR: In this paper, an MOS transistor with 10−nm silicon dioxide as gate insulator and 10 −nm palladium as gate electrode was fabricated and the threshold voltage of this transistor was found to be a function of the partial pressure of hydrogen in the ambient atmosphere.
Abstract: An MOS transistor in silicon with 10−nm silicon dioxide as gate insulator and 10−nm palladium as gate electrode was fabricated. The threshold voltage of this transistor was found to be a function of the partial pressure of hydrogen in the ambient atmosphere. At a device temperature of 150 °C it was possible to detect 40 ppm hydrogen gas in air with response times less than 2 min.

707 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202382
2022153
2021194
2020281
2019345
2018333