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Hardware architecture

About: Hardware architecture is a(n) research topic. Over the lifetime, 10428 publication(s) have been published within this topic receiving 130379 citation(s). The topic is also known as: hardware design model.

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Papers
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Open accessJournal ArticleDOI: 10.1109/MCOM.001.1900107
Qingqing Wu1, Rui Zhang1Institutions (1)
Abstract: IRS is a new and revolutionizing technology that is able to significantly improve the performance of wireless communication networks, by smartly reconfiguring the wireless propagation environment with the use of massive low-cost passive reflecting elements integrated on a planar surface. Specifically, different elements of an IRS can independently reflect the incident signal by controlling its amplitude and/or phase and thereby collaboratively achieve fine-grained 3D passive beamforming for directional signal enhancement or nulling. In this article, we first provide an overview of the IRS technology, including its main applications in wireless communication, competitive advantages over existing technologies, hardware architecture as well as the corresponding new signal model. We then address the key challenges in designing and implementing the new IRS-aided hybrid (with both active and passive components) wireless network, as compared to the traditional network comprising active components only. Finally, numerical results are provided to show the great performance enhancement with the use of IRS in typical wireless networks.

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Topics: Wireless network (63%), Wireless (54%), Hardware architecture (52%)

1,014 Citations


Open accessJournal ArticleDOI: 10.1145/1941487.1941507
Shekhar Borkar1, Andrew A. Chien2Institutions (2)
Abstract: Energy efficiency is the new fundamental limiter of processor performance, way beyond numbers of processors.

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  • Figure 5 outlines the evolution of on-die caches over the past two decades, plotting cache capacity (a) and percentage of die area (b) for Intel microprocessors. At first, cache sizes increased slowly, with decreasing die
    Figure 5 outlines the evolution of on-die caches over the past two decades, plotting cache capacity (a) and percentage of die area (b) for Intel microprocessors. At first, cache sizes increased slowly, with decreasing die
  • Figure 6 divides the cumulative 1,000-fold Intel microprocessor performance increase over the past two decades into performance delivered by transistor speed (frequency) and due to microarchitecture. Almost two-ordersof-magnitude of this performance increase is due to transistor speed alone, now leveling off due to the numerous challenges described in the following sections.
    Figure 6 divides the cumulative 1,000-fold Intel microprocessor performance increase over the past two decades into performance delivered by transistor speed (frequency) and due to microarchitecture. Almost two-ordersof-magnitude of this performance increase is due to transistor speed alone, now leveling off due to the numerous challenges described in the following sections.
Topics: Energy consumption (59%), Efficient energy use (55%), Hardware architecture (55%) ...read more

875 Citations


Open accessProceedings ArticleDOI: 10.1145/1629575.1629589
11 Oct 2009-
Abstract: Modern computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, new byte-addressable, persistent memory technologies such as phase change memory (PCM) offer fast, fine-grained access to persistent storage.In this paper, we present a file system and a hardware architecture that are designed around the properties of persistent, byteaddressable memory. Our file system, BPFS, uses a new technique called short-circuit shadow paging to provide atomic, fine-grained updates to persistent storage. As a result, BPFS provides strong reliability guarantees and offers better performance than traditional file systems, even when both are run on top of byte-addressable, persistent memory. Our hardware architecture enforces atomicity and ordering guarantees required by BPFS while still providing the performance benefits of the L1 and L2 caches.Since these memory technologies are not yet widely available, we evaluate BPFS on DRAM against NTFS on both a RAM disk and a traditional disk. Then, we use microarchitectural simulations to estimate the performance of BPFS on PCM. Despite providing strong safety and consistency guarantees, BPFS on DRAM is typically twice as fast as NTFS on a RAM disk and 4-10 times faster than NTFS on disk. We also show that BPFS on PCM should be significantly faster than a traditional disk-based file system.

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  • Figure 4: Large benchmark execution times. The dashed line for Apache indicates the approximate amount of time in computation.
    Figure 4: Large benchmark execution times. The dashed line for Apache indicates the approximate amount of time in computation.
  • Figure 3: Microbenchmarks showing BPFS performance on appends, random writes, and creates.
    Figure 3: Microbenchmarks showing BPFS performance on appends, random writes, and creates.
  • Figure 7: Projected performance of BPFS-PCM for various levels of sustained throughput.
    Figure 7: Projected performance of BPFS-PCM for various levels of sustained throughput.
  • Figure 1: Sample BPFS file system. The root of the file system isan inode file, which contains inodes that point to directory files and data files. Pointer blocks are shown with two pointers but in reality contain 512.
    Figure 1: Sample BPFS file system. The root of the file system isan inode file, which contains inodes that point to directory files and data files. Pointer blocks are shown with two pointers but in reality contain 512.
  • Figure 5: Speedup of epoch-based caching.
    Figure 5: Speedup of epoch-based caching.
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Topics: File system (60%), Paging (53%), Block (data storage) (51%) ...read more

850 Citations


Open accessJournal ArticleDOI: 10.1109/2.585157
01 Apr 1997-IEEE Computer
Abstract: Fault injection is important to evaluating the dependability of computer systems. Researchers and engineers have created many novel methods to inject faults, which can be implemented in both hardware and software. The contrast between the hardware and software methods lies mainly in the fault injection points they can access, the cost and the level of perturbation. Hardware methods can inject faults into chip pins and internal components, such as combinational circuits and registers that are not software-addressable. On the other hand, software methods are convenient for directly producing changes at the software-state level. Thus, we use hardware methods to evaluate low-level error detection and masking mechanisms, and software methods to test higher level mechanisms. Software methods are less expensive, but they also incur a higher perturbation overhead because they execute software on the target system.

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Topics: Software fault tolerance (70%), Fault injection (63%), Hardware architecture (62%) ...read more

821 Citations


Journal ArticleDOI: 10.1109/MC.2004.175
David Garlan1, Shang-Wen Cheng1, An-Cheng Huang1, Bradley Schmerl1  +1 moreInstitutions (1)
01 Oct 2004-IEEE Computer
Abstract: While attractive in principle, architecture-based self-adaptation raises a number of research and engineering challenges. First, the ability to handle a wide variety of systems must be addressed. Second, the need to reduce costs in adding external control to a system must be addressed. Our rainbow framework attempts to address both problems. By adopting an architecture-based approach, it provides reusable infrastructure together with mechanisms for specializing that infrastructure to the needs of specific systems. The specialization mechanisms let the developer of self-adaptation capabilities choose what aspects of the system to model and monitor, what conditions should trigger adaptation, and how to adapt the system.

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786 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20226
2021326
2020349
2019422
2018385
2017426

Top Attributes

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Topic's top 5 most impactful authors

Liang-Gee Chen

39 papers, 1.3K citations

Sergio Bampi

35 papers, 300 citations

Wayne Luk

32 papers, 325 citations

Nadia Nedjah

25 papers, 199 citations

Ahmed Amine Jerraya

22 papers, 523 citations

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