Topic
Hardware description language
About: Hardware description language is a research topic. Over the lifetime, 6825 publications have been published within this topic receiving 81699 citations. The topic is also known as: HDL.
Papers published on a yearly basis
Papers
More filters
••
16 Nov 2004TL;DR: In this paper, an in-circuit software debug environment is presented, that can be utilized for single- or multi-processor SOCs, and is independent from the chosen technology support, and processor memory or bus architecture configuration.
Abstract: A fundamental feature common to all SOC projects is the inclusion of one or more embedded microprocessors in the design space. As the complexity of algorithms mapped on embedded processors and their interaction with the surrounding SOC resources increase, the availability of reliable software verification means becomes a serious design issue, especially when more than one processor is included in the design. Many existing processor-debugger interfaces are based on specific technology or architectural features such as JTAG interfaces or scan-chains. On the other hand, embedded microprocessor cores are often HDL suites, quite parametric and technology independent, and need to be reused in a very different design environment. In this paper, an in-circuit software debug environment is presented, that can be utilized for single- or multi-processor SOCs. The described methodology, only based on VHDL blocks and software routines, is independent from the chosen technology support, and processor memory or bus architecture configuration.
01 Jan 1999
TL;DR: The top-down design approach is described in this paper for designing a multi-level fuzzy controller.
Abstract: With the rapid increase in size and complexity of digital systems, hardware
description languages, such as VHDL, are quickly becoming the main integral part of
the tools used for advanced digital system design. Although many of the HDL-based
design practices follow bottom-up fashion, the real strength of VHDL is that it
facilitates the top-down design process where high level design concepts can be
described and verified without delving into implementation details. The top-down
design approach is described in this paper for designing a multi-level fuzzy controller
••
30 Sep 2008
TL;DR: This work has as objective to show the design process and implementation of three-degrees of freedom mechanical arm, controlled by a digital system described under VHDL, and implemented into a FPGA (field programmable gate array).
Abstract: This work has as objective to show the design process and implementation of three-degrees of freedom mechanical arm, controlled by a digital system, described under VHDL, and implemented into a FPGA (field programmable gate array). The digital system for control is designed through the interconnection of circuits and functional blocks. The FPGA terminals are used to control the sequences of three stepper motors and this way to achieve the movement of the three-degrees of freedom arm, the interface stage among the control and the motors, is developed with a power electronic circuit based on transistors. This design proposal is a didactic model that seeks to illustrate the stages of the design and, mainly, the digital system for control the movements of the mechanical arm. For this case,the mechanical design of the arm does not depend on a specific trajectory, it is a free trajectory and user can decide, trough the FPGA interface, the mechanical arm movement. The mechanical arm proposal does not have the capacity to exercise big forces, not to lift big weight, but rather it seeks to be an easy construction model and accessible for everyone, since it can be built until with recycled material, just as it was made in this case, for educational purposes.
••
TL;DR: The use of Prolog offers a rare combination of convenient hardware description tools, applications of software techniques in hardware manipulations, and the application of AI concepts.
••
04 Nov 2010TL;DR: This paper studies the design of a parameterized bus interface, and quantitative analysis the parameterized design how effects on IP's reusability compared with nonparameterized design, using LOC (line of code) as a metric.
Abstract: With the rapid development of the designing technology and manufacturing technology about deep submicron of the integrated circuit, SoC(System-on-a-Chip) technology has become the mainstream of integrated circuit design in 21st century, and become current development trend of very large scale integrated circuits. At present, the design of SoC usually adopts the Hierarchization architecture on chip bus, bus interface is the interface of system bus and peripheral bus, and all peripheral IP cores in the SoC go on data communication with processor through interface. For improve the reusability of IP cores, we should improve the configurability of bus interface as much as possible, the parameterized design is a common solution to realize the configurable. This paper studies the design of a parameterized bus interface, and quantitative analysis the parameterized design how effects on IP's reusability compared with nonparameterized design, using LOC (line of code) as a metric.