Hardware description language

About: Hardware description language is a research topic. Over the lifetime, 6825 publications have been published within this topic receiving 81699 citations. The topic is also known as: HDL.

A new approach to pipeline FFT processor

Abstract: A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-2/sup 2/ algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-2/sup 2/ algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log/sub 4/N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL.

Lava: hardware design in Haskell

Abstract: Lava is a tool to assist circuit designers in specifying, designing, verifying and implementing hardware. It is a collection of Haskell modules. The system design exploits functional programming language features, such as monads and type classes, to provide multiple interpretations of circuit descriptions. These interpretations implement standard circuit analyses such as simulation, formal verification and the generation of code for the production of real circuits.Lava also uses polymorphism and higher order functions to provide more abstract and general descriptions than are possible in traditional hardware description languages. Two Fast Fourier Transform circuit examples illustrate this.

Programmable Logic Controllers

Abstract: From the Publisher: Ideal as an accessible introduction for university students, the second edition includes expanded sections on internal architecture, input-output devices, networks, and programming languages with microprocessor systems, and has been fully revised in line with the new BTEC Higher National unit on PLCs, and the 2000 specifications for the Advanced GNVQ unit from Edexcel.

A mathematical approach towards hardware design

Abstract: Today the hardware for embedded systems is often specified in VHDL However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications There is a need of higher level abstraction mechanisms In the embedded systems group of the University of Twente we are working on systematic and transformational methods to design hardware architectures, both multi core and single core The main line in this approach is to start with a straightforward (often mathematical) specification of the problem The next step is to find some adequate transformations on this specification, in particular to find specific optimizations, to be able to distribute the application over different cores The result of these transformations is then translated into the functional programming language Haskell since Haskell is close to mathematics and such a translation often is straightforward Besides, the Haskell code is executable, so one immediately has a simulation of the intended system Next, the resulting Haskell specification is given to a compiler, called CeaSH (for CAES LAnguage for Synchronous Hardware) which translates the specification into VHDL The resulting VHDL is synthesizable, so from there on standard VHDL-tooling can be used for synthesis In this work we primarily focus on streaming applications: ie applications that can be modeled as data-flow graphs At the moment the CeaSH system is ready in prototype form and in the presentation we will give several examples of how it can be used In these examples it will be shown that the specification code is clear and concise Furthermore, it is possible to use powerful abstraction mechanisms, such as polymorphism, higher order functions, pattern matching, lambda abstraction, partial application These features allow a designer to describe circuits in a more natural and concise way than possible with the language elements found in the traditional hardware description languages In addition we will give some examples of transformations that are possible in a mathematical specification, and which do not suffer from the problems encountered in, eg, automatic parallelization of nested for-loops in C-programs

Behavioral consistency of C and Verilog programs using bounded model checking

Abstract: We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program are unwound and translated into a formula that represents behavioral consistency. The formula is then checked using a SAT solver. We are able to translate C programs that include side effects, pointers, dynamic memory allocation, and loops with conditions that cannot be evaluated statically. We describe experimental results on various reactive circuits and programs, including a small processor given in Verilog and its Instruction Set Architecture given in ANSI-C.