Showing papers on "Injection locking published in 2011"

A Sub-100 $\mu$ W MICS/ISM Band Transmitter Based on Injection-Locking and Frequency Multiplication

Abstract: For fully autonomous implantable or body-worn devices running on harvested energy, the peak and average power dissipation of the radio transmitter must be minimized. Additionally, link symmetry must be maintained for peer-to-peer network applications. We propose a highly integrated 90 μW 400 MHz MICS band transmitter with an output power of 20 μW, leading to a 22% global efficiency - the highest reported to date for low-power MICS band systems. We introduce a new transmitter architecture based on cascaded multi-phase injection locking and frequency multiplication to enable low power operation and high global efficiency. Our architecture eliminates slow phase/delay-locked loops for frequency synthesis and uses injection locking to achieve a settling time <;250 ns permitting very aggressive duty cycling of the transmitter to conserve energy. At a data-rate of 200 kbps, the transmitter achieves an energy efficiency of 450 pJ/bit. Our 400 MHz local oscillator topology demonstrates a figure-of-merit of 204 dB while locked to a stable crystal reference. The transmitter occupies 0.04 mm2 of active die area in 130 nm CMOS and is fully integrated except for the crystal and the matching network.

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications

Abstract: This paper proposes a 60 GHz quadrature PLL frequency synthesizer for the IEEE802.15.3c with wide tuning range and low phase noise. The synthesizer is constructed using a 20 GHz PLL that is coupled with a Quadrature Injection Locked Oscillator (QILO) as a frequency tripler to generate the 60 GHz signal. The 20 GHz PLL generates a signal with a phase noise that is lower than -105 dBc/Hz using tail feedback to improve the phase noise while having a 17% tuning range. The proposed 60 GHz QILO uses a combination of parallel and tail injection to enhance the locking range by improving the QILO injection efficiency at the moment of injection and has a 12% tuning range. Both the 20 GHz PLL and the QILO were fabricated as separate chips using a 65 nm CMOS process and measurement results show a phase noise that is less than -95 dBc/Hz@1 MHz at 60 GHz while consuming 80 mW from a 1.2 V supply. To the author's knowledge this phase noise is about 20 dB better than recently reported QPLLs and about 10 dB compared to differential PLLs operating at a similar frequency and at a similar offset.

A Low Energy Injection-Locked FSK Transceiver With Frequency-to-Amplitude Conversion for Body Sensor Applications

Abstract: An energy-efficient 920 MHz FSK transceiver for wireless body sensor network (BSN) applications is implemented in 0.18 μm CMOS technology with 0.7 V supply. A transceiver architecture based on injection-locked frequency divider (ILFD) is proposed for the low energy consumption. In the receiver, the ILFD in the signal path converts the received FSK signal to amplitude-modulated signal which is applied to the next envelope detector. In the transmitter, the ILFD is used as digitally-controlled oscillator (DCO) which directly modulates the FSK signal with digital data. The DCO replaces the frequency synthesizer to eliminate the crystal oscillator (XO), which leads to reduce power consumption and cost. The transceiver can detect whether injection locking occurs or not, and calibrates the frequency drift of DCO over temperature variation thanks to ILFD based architecture. The receiver and transmitter consume 420 μW and 700 μW , respectively, at - 10 dBm output power with a data rate of 5 Mb/s, corresponding to energy consumption of 84 pJ per received bit and 140 pJ per transmitted bit.

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

Abstract: We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.

Injection locking of tunnel junction oscillators to a microwave current

Abstract: Injection locking of a spin transfer nano-oscillator, based on an in-plane magnetized magnetic tunnel junction and generating the frequency f0, to an external signal of varying frequency fe is studied experimentally and with macrospin simulations. It is shown, that if the driving signal has the form of a microwave current, the locking effect is well-pronounced near fe≅2f0, but is almost completely absent near fe≅f0, confirming predictions of analytical theory. It is also shown that noise plays an important role in the locking process, causing the linewidth of the locked oscillation to substantially exceed that of the driving signal.

All-optical memory based on injection-locking bistability in photonic crystal lasers.

Abstract: We have demonstrated an all-optical memory by using InGaAsP/InP buried heterostructure photonic crystal (BH-PhC) lasers. We achieved distinct optical injection locking bistability in an ultra-compact active region (4 × 0.3 × 0.16 μm3) with only 25 μW pump power in the PhC waveguide, which is two orders less than previously reported optical memories based on other bistable semiconductor lasers. Dynamic memory operations were achieved with pump power of 100 μW and switching power of 22 μW and 71 μW in the PhC waveguide. Fast switching times of about 60 ps were achieved. To the authors’ best knowledge, this is the first demonstration of PhC laser-based all-optical memory.

Homodyne Coherent Optical Receiver Using an Optical Injection Phase-Lock Loop

Abstract: We describe the operating principle, practical implementation, and experimental evaluation of a synchronous homodyne coherent optical receiver based on an optical phase-locking scheme that combines optical injection locking of the semiconductor laser local oscillator (LO) with low-speed electronic feedback to give both a large locking bandwidth and a wide tracking range. We demonstrate phase-error variance as low as 0.002 rad2 in 10-GHz bandwidth for locking to a continuous-wave (CW) signal for a combined signal and LO linewidth of 1.5 MHz (full-width at half-maximum), and robust phase locking to a 10-Gb/s binary amplitude-shift-keyed (ASK) signal, enabling synchronous back-to-back demodulation of the signal with low bit error ratio (BER <; 10- 10) and improved performance compared to direct detection at low optical SNR (OSNR). By locking to a low-power CW pilot carrier in the polarization orthogonal to the data signal, demodulation of binary phase-shift-keyed (BPSK) data has been achieved, with the required OSNR at BER = 10-3 reduced by 3 dB compared to demodulation of ASK data under the same conditions. The OSNR penalty after transmission of the ASK and BPSK signals over 40 km of standard single-mode fiber was 1-2 dB at BER = 10-3, indicating that the chromatic dispersion sensitivity of the coherent receiver is similar to that for direct detection, and verifying that the scheme for locking to the orthogonal pilot is applicable to transmission systems, provided that optical polarization tracking is employed. In addition, we demonstrate frequency-selective operation of the coherent receiver, demultiplexing and demodulating one of a pair of equal power, 10 Gb/s, ASK channels separated by 17.5 GHz, with OSNR penalty at BER = 10- 3 of 1.5 dB compared to single-channel operation.

A 90 nm-CMOS, 500 Mbps, 3–5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization

Abstract: A fully-integrated, 3-5 GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90 nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR), requiring only static receiver phase alignment with the transmitted pulses at startup. Transmitter pre-emphasis equalization is utilized to mitigate the effect of multipath on bit-error rate (BER). Occupying 2 mm2 die area, the transceiver achieves a data rate of 500 Mbps, energy efficiency of 0.18 nj/b at 500 Mbps, and a RX raw BER of <; 10-3 across a distance of 10 cm at 125 Mbps. In a real multipath environment, BER improves by 2.35× after equalization of the first multipath reflection.

7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS

Abstract: A high-frequency jitter tolerant receiver in 65 nm CMOS is presented. Jitter tolerance is improved by tracking correlated jitter using a pulsed clock forwarded from the transmitter side. The clock receiver comprises two injection locked oscillators to frequency-multiply, deskew, and adjust jitter tracking bandwidth. Different data rates and latency mismatch between the clock and data paths are accommodated by a jitter tracking bandwidth that is controllable up to 300 MHz. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz.

Polarization Switching in Long-Wavelength VCSELs Subject to Orthogonal Optical Injection

Abstract: Polarization switching (PS) appearing in long-wavelength vertical-cavity surface-emitting lasers (VCSELs) subject to orthogonal optical injection is investigated theoretically and experimentally. We have studied the injected optical power required for PS as a function of the frequency detuning between the injected light and the orthogonal linear polarization of the VCSEL. For a wide range of bias currents applied to the device, the injected power required for the occurrence of PS exhibited a minimum and a plateau with respect to the frequency detuning. The minimum (plateau) was found at negative (positive) frequency detuning. The bistable behavior of the polarization is described. Our experimental results confirm the theoretical predictions of Sciamanna and Panajotov. The levels of the minimum and the plateau were observed to increase as higher bias currents were applied to the VCSEL. A first theoretical and experimental observation of the disappearance and further appearance of PS when increasing the injected power in long-wavelength VCSELs is described. This situation is obtained for small levels of negative frequency detuning and for large enough values of applied bias current. A good overall qualitative agreement is found between our theoretical and experimental results.

A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS

Abstract: Burst-mode clock and data recovery circuits (BMCDR) are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for several burst sequences, each originating from a different source. As a result, the BMCDR is required to lock to an incoming data stream within tens of UIs (for example 40ns in GPON). Previous works use either injection locking [3, 4] or gated VCO [5, 6] to achieve this fast locking. In both cases, the control voltage of the CDR's VCO is generated by a reference PLL with a matching VCO to guarantee accurate frequency locking. However, any component mismatch between the two VCO's results in a frequency offset between the reference PLL frequency and the CDR's VCO frequency, and hence in a reduction of the CDR's tolerance for consecutive identical digits (CID). For example, [7] reports a frequency offset of over 20MHz (2000ppm) for 10Gb/s operation. We present a BMCDR that is based on phase interpolation (PI), eliminating the possibility of local frequency offset between the reference and recovered clock. We demonstrate 1 to 6Gb/s operation in 65nm CMOS with a locking time of less than 1UI.

Spin Torque Oscillators and RF Currents—Modulation, Locking, and Ringing

Abstract: We study the interaction between a nano-contact spin torque oscillator (STO) and injected radio-frequency and microwave currents. Modulation of the STO signal is observed over a wide frequency range from 100 MHz to 3.2 GHz. The modulation sidebands agree well with macrospin simulations. When the injected microwave frequency approaches that of the STO, we observe injection locking, frequency pulling/pushing, and intermodulation peaks. While the intermodulation peaks are reasonably well reproduced by macrospin simulations, they do not follow the Adler's model. We argue that this discrepancy is due to intrinsic ringing effects stemming from the internal dynamics of the STO.

A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter

Abstract: A novel technique for mitigation of self interference in a highly integrated SoC transmitter is presented. The interference originates from the internal power amplifier (i.e., aggressor) that leads to injection pulling of the local RF oscillator (i.e., victim). The characteristic of injection pulling was found to be dependent on the AM signal applied to the power amplifier. A hypothesis describing the mechanism of injection pulling of the local oscillator is presented. A mathematical model is developed to study the characteristics of this self interference verified then by measurements. Based on this model, a digitally controlled delay circuit is proposed and implemented in a digital polar GSM/EDGE transmitter that makes the system less susceptible to injection pulling through automatic phase adjustment between the aggressor and the victim. Compliant EVM and spectrum performance is measured on SoC fabricated in 65-nm CMOS showing the effectiveness of the proposed solution.

Cognitive Polar Receiver Using Two Injection-Locked Oscillator Stages

Abstract: A novel cognitive polar receiver that utilizes two injection-locked oscillator stages to extract the modulation envelope and phase components of a received nonconstant envelope modulation signal without using phase-locked-loop-based carrier recovery circuitry is presented. The paper begins with a theoretical analysis of injection locking and pulling phenomena based on the discrete-time computation approach, and then develops the principles of the proposed receiver. The implemented prototype can cover a sensing bandwidth of 140 MHz at a central frequency of 2.43 GHz and perform π/4 differential quadrature phase-shift keying and quadrature phase-shift keying demodulation with the best error vector magnitudes of 6.6% and 7.9%, respectively, both at a symbol rate of 2 Ms/s. Due to its simplicity, the proposed receiver has great potential as an energy-efficient architecture with low complexity for short-range wireless communications.

A simple, unified phase noise model for injection-locked oscillators

Abstract: This paper presents a simple, unified phase noise model for injection-locked oscillators (ILO). We show that an ILO is identical to a type-I first-order PLL in its noise behavior within the lock range. The model predicts the phase noise of injection-locked oscillators (ILO), injection-locked frequency dividers (ILFD), and injection-locked frequency multipliers (ILFM) as a function of the injection source phase noise and the oscillator phase noise. Measurement results from a discrete 57MHz Colpitts ILO, an integrated 6.5GHz ILFD, and an integrated 24GHz ILFM are presented to validate the theoretical predictions.

Realization of All-Optical Digital Comparator Using Single Mode Fabry–Pérot Laser Diodes

Abstract: A two-bit all-optical digital comparator using single mode Fabry-Perot laser diodes (SMFP-LDs) at an input data rate of 10 Gbps is proposed and demonstrated. All-optical comparator is demonstrated using cascaded logic units which are based on injection locking, multi-input injection locking and supporting beam principles for suppressing the dominant mode of SMFP-LDs. Digital comparators are the key components for the decision making circuits, the integral part of the arithmetic and logical units of optical data processors. The output performance of the proposed all-optical comparator is verified with output waveform, rising-falling time, output eye diagram, and bit error rate (BER) at 10 Gbps input Non Return to Zero (NRZ) PRBS of 231-1 signal. The rising/falling time of about 47 ps, clear output waveforms, and clear output eye diagram with an extinction ratio of about 12 dB are obtained. A maximum power penalty of 1.3 dB is measured at a BER of 10-9.

A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz

Abstract: With a cut-off frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation at mm-Waves is extremely large. To save power, recently reported mm-Wave PLLs propose tunable narrowband dividers, based on injection-locking techniques, together with digital calibration algorithms [1,2]. On the other hand, for division factors higher than 2, the frequency locking range of injection-locked oscillators is very limited, mandating fine and frequent calibrations. This paper introduces clocked differential amplifiers, working as dynamic CML latches, to realize high speed and low power mm-Wave dividers. The solution is very compact, which is particularly desirable at mm-Waves to ease chip layout and shorten IC interconnections, minimizing signal losses. A frequency divider-by-4 has been realized in a 65nm bulk CMOS technology and prototypes prove an operating frequency programmable from 20 to 70GHz. The frequency range in each sub-band spans from 10% to 17%, corresponding to a 2.5x to 4x improvement compared to injection-locked dividers-by-4. Maximum power dissipation is 6.5mW and occupied area is only 15μm × 30μm.

Frequency-Hopped Quadrature Frequency Synthesizer in 0.13- $\mu$ m Technology

Abstract: This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only implementation and has been fabricated in a 0.13-μm SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.

Demonstration of All-Optical nand Gate Using Single-Mode Fabry–Pérot Laser Diode

Abstract: A novel, simple, and universal all-optical NAND gate using single-mode Fabry-Perot laser diode (SMFP-LD) is demonstrated. The basic operating principle of the proposed NAND gate is the modulation of the dominant lasing mode of SMFP-LD by the injection of external beams. The dominant lasing mode gain is suppressed only when both input beams are high. As SMFP-LD is used to demonstrate the logic function, no additional beam is required as needed in the multimode Fabry-Perot laser diode (MMFP-LD) schemes. The operating principle is explained and the experimental results are presented at 10 Gb/s input data. The logic function is realized with a clear eye opening and an extinction ratio of 14.6 dB with a rising and falling time of 38.3 and 67.1 ps, respectively.

Beyond-Bandwidth Electrical Pulse Modulation of a TO-Can Packaged VCSEL for 10 Gbit/s Injection-Locked NRZ-to-RZ Transmission

Abstract: The parametric characterization of a nonreturn-to-zero (NRZ) to return-to-zero (RZ) data format converter based on the external optical NRZ injection of a TO-46-can packaged vertical-cavity surface-emitting laser (VCSEL) directly modulated by a 10 GHz electrical pulse is demonstrated. The electrical-pulse modulation induced gain switching of the VCSEL is initiated under external optical NRZ data injection that increases the relaxation oscillation frequency of the homemade VCSEL from 2.2 to 7.4 GHz, thereby enabling its electrical modulation bandwidth up to 10 GHz. The external NRZ injection reduces the lasing threshold and enlarges the modulation depth of the VCSEL so that the converted RZ data pulsewidth can be shortened to 27 ps with a slightly increased peak-to-peak negative frequency chirp of 4.3 GHz (corresponding to a chirp parameter of 122 MHz/ps). The chirp and bit error rate (BER) display strong correlations with the injection power and the biased current of the VCSEL. With external injection, the receiving power required for achieving a BER below 10-9 at 10 Gbit/s is -19.5 dBm, and a power penalty of 16 dB is observed when the dc bias of the electrical-pulse modulated VCSEL is decreased by only 10% from the threshold condition.

Realization of all-optical multi-logic functions and a digital adder with input beam power management for multi-input injection locking in a single-mode Fabry-Pérot laser diode.

Abstract: We propose a novel idea for the suppression of the dominant mode of the single-mode Fabry-Perot laser diode (SMFP-LD) to realize all-optical multi-logic functions and a digital adder. The basic principle of the proposed scheme is the power management of input beams to suppress the dominant mode of the SMFP-LD for multi-input injection locking. The proposed principle is explained and implemented to realize all-optical multi-logic functions and a digital adder at an input data rate of 10 Gbps. A clear eye opening with an extinction ratio of about 12 dB and a rising-falling time of less than 40 ps are observed at the outputs. The bit error rate (BER) performance is measured for all logic gates and half adder operation. We found there is no BER floor up to BER of 10−12 and the maximum power penalty of about 1.2 dB at a BER of 10−9.

Spur-free all-digital PLL in 65nm for mobile phones

Abstract: After the first-ever all-digital PLL (ADPLL) [1] for Bluetooth radios has proven benefits of CMOS scaling and integration, demonstrators for more challenging wireless standards have emerged [2–6]. In the ADPLL, however, the digitally-controlled oscillator (DCO) and time-to-digital converter (TDC) quantize the time and frequency tuning functions, respectively, which can lead to spurious tones and phase noise increase. As such, finite TDC resolution can distort data modulation and spectral mask at near integer-N channels, while finite DCO step size can add far-out spurs and phase noise. Also, a major underreported issue is an injection pulling of the DCO due to harmonics of the digital activity at closely-spaced frequencies, which can also create spurs. This work addresses all these problems and demonstrates RF performance matching that of the best-in-class traditional approaches.

A Millimeter-Wave CMOS Triple-Band Phase-Locked Loop With A Multimode LC-Based ILFD

Abstract: A millimeter-wave multiband phase-locked loop (PLL) is presented for the first time, which covers 40-, 60-, and 80-GHz bands. Three voltage-controlled oscillators corresponding to different frequencies are input to a multiband injection-locked frequency divider and switched on one at a time by a multiplexer as a band selector. The feedback loop embraces the following components: a chain of dividers with a fixed division-modulus of 256, a phase-frequency detector, a charge-pump, and a second-order loop filter. The PLL is clocked by a reference frequency of 78 MHz and its output power is higher than -9.5 dBm. The phase noise is -103 dBc/Hz at an offset frequency of 10 MHz. With a supply voltage of 1.5 V, the entire PLL consumes 114 mW. The chip is implemented in a 90-nm CMOS technology and measures 1.12 mm2.

On the Synchronization Condition for Superharmonic Coupled QVCOs

Abstract: A steady-state nonlinear analysis of quadrature voltage-controlled oscillators (QVCOs) comprising two VCOs mutually coupled at their second-harmonic frequency through a direct coupling circuit is presented. The analysis is based on an accurate prediction of the behavior of each VCO, which is analyzed separately as an injection locked oscillator taking into account both higher order harmonics of the differential tank voltage and the effect of the common-mode voltage at the drain terminals. We show that synchronization of the two VCOs is possible only at a frequency, derived in closed-form, which differs appreciably from the tank's resonant frequency.

A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistribution

Abstract: Phased-array receivers provide two major benefits over single-antenna receivers [1]. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking [2], phase selection [3] and vector modulation [1,4,5,6]. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge-redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.

A Wideband Millimeter-Wave Frequency Synthesis Architecture Using Multi-Order Harmonic-Synthesis and Variable $N$ -Push Frequency Multiplication

Abstract: This paper proposes an architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband millimeter-wave frequencies. The first step is implemented using a multi-order digital harmonic synthesis block combined with a multi-phase injection-locked oscillator. A variable N-push frequency multiplier uses the output of the oscillator to implement the second harmonic generation step. A prototype of the proposed system is designed and fabricated in 90 nm CMOS technology. Measurements show that using a phase-locked input signal of 1-1.43 GHz, the system can provide an output which covers the frequency range of 5-32 GHz. This represents a tuning bandwidth of 27 GHz with a tuning range of 146%. The measured phase noise at 1 MHz offset is -116 dBc/Hz and -99 dBc/Hz at 5 GHz and 32 GHz, respectively.

Mutual Injection Locking of Monolithically Integrated Coupled-Cavity DBR Lasers

Abstract: We present a photonic integrated circuit (PIC) composed of two strongly coupled distributed Bragg reflector (DBR) lasers. This PIC utilizes the dynamics of mutual injection locking to increase the relaxation resonance frequency from 3 GHz to beyond 30 GHz. Mutual injection-locking and external injection-locking operation are compared.

Effective homodyne optical phase locking to PSK signal by means of 8b10b line coding

Abstract: We demonstrate a novel technique that allows effective homodyne optical phase locking to a phase shift keying (PSK) signal with a residual carrier. We exploit 8b10b coding of the signal in order to reduce its low frequency spectral content, suppressing the data-to-phase crosstalk effect. In a transmission experiment on a 10 Gb/s binary PSK signal (8 Gb/s before coding), we achieved transmission over 215 km of dispersion-compensated, installed single-mode fibre, with no penalty compared to back-to-back at a bit error ratio of 10−3. The proposed solution is applicable to other modulation formats, including multi-level amplitude and/or phase modulation formats.

A study of superharmonic injection locking in multiband frequency dividers

Abstract: A superharmonic voltage-controlled injection-locked frequency divider, implemented using a modified Colpitts oscillator operating at 2.5, 5 and 10 GHz and a cross-coupled LC oscillator operating at 1.25, 2.5 and 5 GHz, is demonstrated. The proposed triple-band operation is achieved by employing a novel technique that uses pin-diodes and negative power supply. The discrete dividers, built with low noise hetero-junction FETs and high-frequency SiGe BJTs, are described theoretically while their functionality is proven experimentally. Additionally, a short phase noise analysis, which is missing in the literature, is given. Phase noise, frequency range of operation, and locking range measurement results are presented. Finally, post-layout simulation results of a 5 GHz fully differential injection-locked frequency divider, implemented in a 0.25µm SiGe process are provided. Copyright © 2010 John Wiley & Sons, Ltd.