Injection locking

About: Injection locking is a research topic. Over the lifetime, 4567 publications have been published within this topic receiving 60942 citations.

A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS

Abstract: Burst-mode clock and data recovery circuits (BMCDR) are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for several burst sequences, each originating from a different source. As a result, the BMCDR is required to lock to an incoming data stream within tens of UIs (for example 40ns in GPON). Previous works use either injection locking [3, 4] or gated VCO [5, 6] to achieve this fast locking. In both cases, the control voltage of the CDR's VCO is generated by a reference PLL with a matching VCO to guarantee accurate frequency locking. However, any component mismatch between the two VCO's results in a frequency offset between the reference PLL frequency and the CDR's VCO frequency, and hence in a reduction of the CDR's tolerance for consecutive identical digits (CID). For example, [7] reports a frequency offset of over 20MHz (2000ppm) for 10Gb/s operation. We present a BMCDR that is based on phase interpolation (PI), eliminating the possibility of local frequency offset between the reference and recovered clock. We demonstrate 1 to 6Gb/s operation in 65nm CMOS with a locking time of less than 1UI.

A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator

Abstract: Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lock-in time should be within the period of several tens of bits. Therefore, the PLL-based phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s) and 2× power efficiency [2.4mW/(Gb/s)] of previous fast-lock continuous-rate CDRs [3, 4].

A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique

Abstract: The design and experimental verification of a 20Gb/s CDR circuit based on injection-locking technique is presented. Fabricated in 90nm CMOS technology, this circuit achieves a BER of <10-9 for both continuous and burst modes. It has tunability of over 800Mb/s while consuming 175mW. The re-acquisition time of this CDR is 1b interval.

Mutual Pulling Between Two Oscillators

Abstract: Behavior of two mutually coupled phase-locked or free-running oscillators with nearby frequencies is studied. In the case of two free-running mutually coupled oscillators, the two oscillators are either locked to a common frequency, or they undergo through a mutual pulling interaction. It is shown that center frequencies of the pulled oscillators come closer, however, they do not necessarily approach toward each other from opposite directions. It is also demonstrated that the strengths of mutual injections as well as the phase-shifts experienced by the mutually injected signals, affect locations of the two center frequencies. The paper also studies impacts of phase-locked loops on the location and magnitude of the sidebands, when the two mutually coupled oscillators are phase-locked. Effects of the phase-shifts endured by the mutually injected signals on the sidebands are also discussed.