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Integral nonlinearity
About: Integral nonlinearity is a research topic. Over the lifetime, 1295 publications have been published within this topic receiving 21919 citations.
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TL;DR: In this article, a 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 /spl mu/m CMOS technology is presented.
Abstract: A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 /spl mu/m CMOS technology is presented. It is based on a current steering doubly segmented 6+2+4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSB's), respectively. The measured glitch energy is 1.9 pV.s. For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV.s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm/sup 2/.
349 citations
07 Aug 2002
TL;DR: Digital calibration using adaptive signal processing corrects offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10b 120MSample/s pipelined ADC.
Abstract: Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm/sup 2/, and the power dissipation is 234 mW from a 3.3-V supply.
348 citations
TL;DR: A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration with Adaptive signal processing and extra resolution in each channel is designed and fabricated in a 1 /spl mu/m CMOS technology.
Abstract: A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 /spl mu/m CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm/sup 2/, and the power dissipation is 565 mW from a 5 V supply.
342 citations
TL;DR: In this article, a general noise-shaping DAC architecture along with two special-case configurations that achieve first and second-order noise shaping, respectively, are presented, and a rigorous explanation of the apparent paradox of how DAC noise can be spectrally shaped even though the sources of the DAC noise-the errors introduced by the analog circuitry-are not known to the noiseshaping algorithm.
Abstract: Recently, various multibit noise-shaping digital-to-analog converters (DACs) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DACs have the potential to significantly increase the present precision limits of /spl Delta//spl Sigma/ data converters by eliminating the need for one-bit quantization in delta-sigma modulators. This paper extends the practicality of the noise-shaping DAC approach by presenting a general noise-shaping DAC architecture along with two special-case configurations that achieve first- and second-order noise-shaping, respectively. The second-order DAC configuration, in particular, is the least complex of those currently known to the author. Additionally, the paper provides a rigorous explanation of the apparent paradox of how the DAC noise can be spectrally shaped even though the sources of the DAC noise-the errors introduced by the analog circuitry-are not known to the noise-shaping algorithm.
321 citations
TL;DR: The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption to achieve 14-b accuracy without calibration or dithering.
Abstract: This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V.
302 citations