Integral nonlinearity

About: Integral nonlinearity is a research topic. Over the lifetime, 1295 publications have been published within this topic receiving 21919 citations.

A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method

Abstract: This paper describes a time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 mus dynamic range suitable for laser range-finding application for example. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive signals using binary search. The method utilizes a pair of digital-to-time converters (DTC), the propagation delay difference between which is implemented by digitally controlling the unit load capacitors of their delay cells, thus enabling sub-gate delay timing resolution. The rms single-shot precision, i.e., standard deviation sigma-value of the TDC is 3.2 ps, which is achieved by using an external integral nonlinearity look-up table (INL-LUT) for the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 mum CMOS process.

1-V 9-bit pipelined switched-opamp ADC

Abstract: A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-/spl mu/m CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V, the clock frequency can be increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW.

A 15 b 5 MSample/s low-spurious CMOS ADC

Abstract: A 5-5-5-6-b pipelined analog-to-digital converter (ADC) architecture alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-b most significant bit (MSB) stages are digitally calibrated to implement a 15-b, 5-Msample/s low-spurious ADC using 1.4-/spl mu/m CMOS. A skip-and-fill algorithm with nonlinear interpolation also opens up the possibility of calibrating ADC's in the background synchronously with their normal operation. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.75/-0.6 least significant bit (LSB), an integral nonlinearity (INL) of +1.77/-1.58 LSB, and all spurious components are suppressed to below -93 dB when sampled at 5 MHz. The chip occupies 27 mm/sup 2/, and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing.

Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits

Abstract: This paper describes a new built-in self test (BIST) technique suitable for both functional and structural testing of analog and mixed-signal circuits based on the oscillation-test methodology. Analog-to-digital converter (ADC) is used as a test vehicle to demonstrate the capability of the proposed OBIST technique for both functional and structural testing. Design of different parts of OBIST structure is also presented. The ADC conversion rate, differential nonlinearity (DNL) and integral nonlinearity (INL) at each quantization band edge (QBE) are tested as functional parameters. These parameters are considered to be the most important functional characteristics of an ADC. Practical experimentation using real-world successive approximation and flash ADCs confirms the accuracy of OBIST for functional testing of ADCs. Simulation results using a 3-bit flash ADC designed using a CMOS 1.2 /spl mu/m technology are also presented. For structural testing, oversampled sigma-delta ADCs are investigated. Both hard and soft faults are considered and some simulation results are presented.

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

Abstract: A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.