Integrated circuit

About: Integrated circuit is a research topic. Over the lifetime, 82735 publications have been published within this topic receiving 1053525 citations. The topic is also known as: IC & chip.

Modeling, Design, and Verification for the Analog Front-End of a MEMS-Based Parallel Scanning-Probe Storage Device

Abstract: We present an integrated analog front-end (AFE) for the read-channel of a parallel scanning-probe storage device. The read/write element is based on an array of microfabricated silicon cantilevers equipped with heating elements to form nanometer-sized indentations in a polymer surface using integral atomic-force microscope (AFM) tips. An accurate cantilever model based on the combination of a thermal/electrical lumped-element model and a behavioral model of the electrostatic/mechanical part are introduced. The behavioral model of the electrostatic/mechanical part is automatically generated from a full finite-element model (FEM). The model is completely implemented in Verilog-A and was used to co-develop the integrated analog front-end circuitry together with the read/write cantilever. The cantilever model and the analog front-end were simulated together and the results were experimentally verified. The approach chosen is well suited for system-level simulation and verification/extraction in a design environment based on standard EDA tools.

Transmitter and receiver impedence control using shunt switches

Abstract: Circuits, methods, and apparatus that provide isolation between receive and transmit circuits in a wireless transceiver. One example provides switches that can be included on an integrated circuit with at least portions of a wireless transceiver. These switches vary the impedance of transmitter and receiver circuits between a termination impedance and a high impedance by inserting or removing components in parallel with matching networks. Signal losses are minimized since these switches are shunt connected to input and output paths on the wireless circuit and are not connected directly in either signal path.

Improved method of planarization of topologies in integrated circuit structures

Abstract: A method is disclosed for making a highly planar­ized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit struc­ture, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etch­ing exposed portions of said conformal oxide layer through the mask openings down to a level approxi­mately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer re­gaining after the etching step to form a highly planarized structure. Optionally, the oxide layer may be further etched anisotropically until the upper surfaces of the underlying integrated circuit structure is exposed.

Method for coupling to semiconductor device in an integrated circuit having edge-defined sub-lithographic conductors

Abstract: An integrated circuit comprising stacked capacitor memory cells having sub-lithographic, edge-defined word lines and a method for forming such an integrated circuit. The method forms conductors adjacent to sub-lithographic word lines in order to couple a stacked capacitor to the access transistor of the memory cell. The conductors are bounded by the word lines. The bit line and capacitor are formed with a single mask image in such a manner as to self-align the bit line and the capacitor and to maximize the capacitance of the memory device. The method may be used to couple any suitable circuit element to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic word lines.

Modeling of lead-frame plastic CSPs for accurate prediction of their low-pass filter effects on RFICs

Abstract: This paper presents a direct extraction method to construct the electrical models of lead-frame plastic chip scale packages for RF integrated circuits (RFICs) from the measured S-parameters To evaluate the package effects on the reciprocal passive components, the insertion and return losses for an on-chip 50-/spl Omega/ microstrip line housed in a 32-pin bump chip carrier (BCC) package were analyzed based on the established package model Excellent agreement with measurement has been found up to 15 GHz When applied to the nonreciprocal active components, the gain variations for a heterojunction-bipolar-transistor array housed in an 8-pin BCC package have also been successfully predicted up to 22 GHz Both cases have demonstrated that the package acts as a low-pass filter to cause a sharp cutoff for the RFIC components above a certain frequency