Showing papers on "Interface (computing) published in 1975"

Switching system for non-symmetrical sharing of computer peripheral equipment

Abstract: Switching apparatus and methods are disclosed by which one or more secondary computers of a loosely-coupled multiprocessing system may communicate directly with selected items of active peripheral equipment of a main computer of the system. This invention, which is an improvement over device-sharing means and indirect-accessing methods of the prior art, may be applied to existing computer systems without modification to any element of their hardware and without modification to the operating system software of the main computer. An essentially autonomous "intelligent switch," connected to an input/output interface (bus) of each processor and completely transparent to the main processor, is used to switch one or more items of operating peripheral equipment from the main computer to a secondary computer in response to asynchronous service requests from the secondary computer. Two modes of operation are provided: Interface Capture and Data Capture. Interface Capture provides a means for temporarily borrowing items of peripheral equipment having off-line operating capabilities, such as buffered line-printers, and is performed during a normal off-line operation of such equipment. With Interface Capture, the requesting secondary computer obtains complete control of the captured item of peripheral equipment for an arbitrary period of time. Data Capture, on the other hand, is designed for use primarily with direct-access auxiliary storage devices and is performed while a device is executing a read or write operation initiated by the main computer. Data Capture provides a secondary computer with the means for directly accessing shared data space in auxiliary storage without, however, requiring the secondary computer to duplicate or replicate the access-method software and input/output hardware capabilities of the main computer system. Instead, the secondary computer draws parasitically upon the hardware and software resources of the main computer to access the requested data space. Unlike indirect-accessing methods of the prior art, however, this is accomplished without burdening the main processor, its main storage, and its input/output channels with the overhead tasks of buffering data blocks and dispatching data to or from the requesting secondary computer.

Data transmission systems

Abstract: A data transmission system for interfacing a computer with a plurality of data sources which are in groups, each group at an individual remote location, comprising local interface apparatus for the computer and remote interface apparatus for each remote location, wherein individual sending and receiving means at the local apparatus are provided for connection by a two-wire channel to sending and receiving means at each remote apparatus, wherein the local apparatus includes a buffer for each channel to receive input data words one at a time in bit serial form its respective channel, means for polling each buffer in turn until a buffer having an input data word is located when polling stops, and means responsive to an input by the computer of an input data word from a buffer to clear that buffer, send an acknowledge word in bit serial form to the respective remote location and restart the polling.

Fault processor for programmable controller with remote I/O interface racks

Abstract: A programmable controller includes four remotely located input/output interface racks which are connected by cables to an I/O scanner circuit which is centrally located with the controller processor and memory. Input and output data is serially transmitted between the I/O scanner circuit and the interface racks, and fault processors are located in both the I/O scanner circuit and the interface racks to monitor the operation. The fault processors include fault tolerant detector circuits which ignore erroneous transmissions caused by industrial noise, but which initiate a shutdown process when malfunctions occur. The shutdown process is controlled by a programmable disabling circuit which is responsive to program instructions stored in the controller memory to allow independent, quasi-independent, or dependent operation of the machines connected to each of the four interface racks.

Input devices for interactive graphics

Abstract: Interactive graphic systems provide the potential for natural and efficient manmachine communication. In order to exploit fully this potential and provide a conceptually simple man-computer interface, the graphic input and output devices must be closely integrated. This paper classifies and surveys the basic peripheral hardware, in particular that relevant to graphic data entry, and relates the merits of each device to the interaction process.

Programmable interface controller for numerical machine systems

Abstract: A programmable interface controller capable of assuming specific sequential control functions is disclosed. The disclosed controller is a slave device under the direct control of the numerical control computer and is effectively transparent to numerical control machine system. Upon a first command the interface controller receives and stores data from the numerical control computer. The stored data is processed in accordance with an internal program and the results of the processing temporarily stored therein. Upon a second command, the results of the processing are returned to the numerical control computer from where they are distributed via the systems bi-directional bus to the machine as well as to operating routines elsewhere in the numerical control system. The programmable interface controller performs Boolean and logic arithmetic on the data received from the numerical control computer and is capable of assuming the control functions of prior art magnetics as well as other sequential control functions normally performed by the numerical control computer.

Asynchronous status interlock circuit for interface adaptor

Abstract: An asynchronous interlock circuit for an interface adaptor circuit in a digital system includes a D-type latch, a D-type flip-flop, and an RS-type flip-flop interconnected to accept a peripheral status input from a peripheral equipment unit, a read status input and a read data input derived from control and selection inputs to the interface adaptor from a microprocessor unit of the digital system. The asynchronous interlock circuit stores information corresponding to a logical "1" on the peripheral status interrupt input in the D-type flip-flop, even if the latter signal disappears prior to acknowledgment by the microprocessor of a corresponding interrupt signal generated by the interface adaptor circuit. The D-type flip-flop is reset by a sequence of a read status signal and a read data signal, thereby avoiding problems which could arise if the peripheral status input remains at a logical "1" even after acknowledgment by the microprocessor unit of an interrupt signal generated by the interface adaptor. If a status change occurs on the peripheral status input while status is being read, the D-type latch is inhibited and the status change is not accepted until the read status operation is complete. RELATED APPLICATIONS This application is related to assignee's copending U.S. patent application Ser. No. 519,138 "Interface Adaptor Architecture", Ser. No. 519,150 "Microprocessor Architecture", and Ser. No. 519,149 "Microprocessor System" by Bennett et al., all filed on Oct. 30, 1974, and to assignee's copending U.S. patent applications, "Asynchronous Communications Interface Adaptor", Ser. No. 550,336, "Logic Circuitry for Selection of Dedicated Registers", Ser. No. 550,338, "Interrupt Status Indication Logic for Polled Interrupt Digital System", Ser. No. 550,340, and "Digital System with Peripheral Control of Interface Adaptor", Ser. No. 550,311, all by Hepworth et. al. BACKGROUND OF THE INVENTION A large number of minicomputers are presently available. More recently, microcomputers utilizing bidirectional data busses have become available. A variety of specialized circuits in integrated circuit form have been utilized to interface between such bidirectional data busses and a variety of peripheral devices controlled by and interacting with microcomputers, such as, keyboards, printers, control displays, readers, plotters, etc. Circuits have also been provided to interface between bidirectional data busses and modems (modulator-demodulator) to allow the microcomputer to control remote equipment over a telephone line by converting data in a parallel word format to a serial word format, supplying signals representing the serial word format to a modem which sends data over a telephone line. Such modem circuits also receive data in a serial format from a telephone line, and transfer the data to an adaptor circuit which changes the data from the serial word format to a parallel word format and write it onto the bidirectional data bus. The MOS (metal-oxide-semiconductor) technology has been utilized to provide a microcomputer using microprocessor unit chips (MPU's) integrated on a single semiconductor chip. Integrated circuit random access memory chips (RAM) and read only memory (ROM) chips and suitable interface adaptor chips for coupling the bidirectional data bus to peripheral equipment have also been provided by the MOS technology. Thereby, the power of computer data processing is made available at very low cost for use in a wide variety of industrial communications equipment. However, to take advantage of such low cost microcomputer systems to the fullest extent, it is often necessary to provide an efficient means of interfacing between the system data bus and peripheral devices which transmit and receive data asynchronously. In the past, in order to permit communication between a bidirectional data bus and, for example, a modem, integrated circuits capable of providing both serial-to-parallel conversion for a receiving section thereof and parallel-to-serial conversion for a transmitting section thereof on a single chip, along with formating circuitry have been utilized. It has been necessary to provide additional complex bus interface circuitry, separate from said chip, which is capable of receiving data from and transmitting data onto the bidirectional data bus and accepting or receiving data from said chip. This has required additional semiconductor packages, lower component density of the final product, and consequently higher costs.

Computer input/output control apparatus

Abstract: Apparatus for the flexible coupling of peripheral units to a digital computer system, wherein any input/output port of the system is capable of communicating with a peripheral unit over various forms of interface

Control apparatus for controlling data flow between a control processing unit and peripheral devices

Abstract: A peripheral controller capable of simultaneously handling data transfer microprocesses for several different peripheral devices. The controller includes a set of memories, logic circuits and a physical interface channel for transmitting data between a control processing unit and the peripheral controller and for transmitting data between the peripheral controller and the peripheral devices, an interface control unit for enabling a predetermined one of the peripheral devices to communicate with the peripheral controller, a memory for storing microprograms for controlling the data flow between the control processing unit and the peripheral devices, and a processing circuit for administering the sharing of the processing time of the peripheral controller between the plurality of peripheral devices and the control processing unit.

Apparatus for control and data transfer between a serial data transmission medium and a plurality of devices

Abstract: APPARATUS FOR CONTROL AND DATA TRANSFER BETWEEN A SERIAL DATA TRANSMISSION MEDIUM AND A PLURALITY OF DEVICES Abstract of the Disclosure Apparatus under microprocessor control for use in communicating over a serial communication loop with a remote attached control unit. It is capable of establishing frame synchronization, interpreting commands, assembling data and transmitting bits on the loop. The apparatus also communicates with I/O devices over a demand/response interface.A microprocessor interface with the loop includes loop sync control which establishes bit synchronization and generates a restart pulse at bit receive time and bit send time. The execution of instructions by the micro-processor is stopped and the microprocessor enters a wait state when it has finished all previous work and is ready to receive a loop bit. When it is time to receive the loop bit the microprocessor is restarted in response to the restart pulse from the loop synchronization.or output operations to a device, the microprocessor loads the device address and a device command or data into shift registers and ini-tiates the transfer by setting a latch. When the transfer to the device is completed, this latch is reset in response to a signal from the device.

An Optical/Digital Processor: Hardware and Applications

Abstract: A real-time two-dimensional hybrid processor consisting of a coherent optical system, an optical/digital interface, and a PDP-11/15 control minicomputer is described. The input electrical-to-optical transducer is an electron-beam addressed potassium dideuterium phosphate (KD 2 PO 4 ) light valve. The requirements and hardware for the output optical-to-digital interface, which is constructed from modular computer building blocks, are presented. Initial experimental results demonstrating the operation of this hybrid processor in phased array radar data processing, synthetic aperture image correlation, and text correlation are included. The applications chosen emphasize the role of the interface in the analysis of data from an optical processor and possible extensions to the digital feedback control of an optical processor.

Data communication system having bidirectional station interfaces

Abstract: Digital data, in the form of serial station bit frames which exclude protocol information, are communicated bidirectionally over a plurality of serial transmission channels to peripheral devices in a digital process control system. Data enters and leaves a process control computer input-output section serially in response to software-generated control signals. Serial-to-parallel station interfaces are located along each channel. Each interface has a multifunctional shift register responding to the control signals to provide not only bidirectional data flow through each station, but simultaneous parallel loading of each peripheral device. One software control logic arrangement eliminates modems and portions of hardwired data flow control logic elements in each station interface, yet operates with a station bit frame which excludes protocol information. Also provided are true interrupt capability at each interface; verification of every bit of input and/or output of each station interface; diagnostics.

Artificial Intelligence - Research and Applications

Abstract: : This report describes the work to develop a computer based consultant (CBC) system. The system is being designed to talk (in ordinary English) with a human user to help him perform tasks entailing maintenance and troubleshooting of electromechanical equipment. Our current (April 1975) demonstration system is a base for future systems and already illustrates abilities to interact with an apprentice to help him assemble a small air compressor. The body of the report is divided into two major sections. One of these describes the technology behind the April 1975 demonstration system. The other describes work in progress that will contribute to the power and versatility of future demonstration systems. Our 1975 system has the following specific abilities: It can generate and execute plans for assembly/disassembly at several levels of detail. It can answer queries from the apprentice about the status of the equipment. It can point at parts of the compressor and can name parts pointed to by the apprentice. It has a rudimentary ability for two-way communication using speech. The basis for each of these is described in detail. Work supporting subsequent systems has been in the area of natural language understanding, modeling, troubleshooting, and vision. The report also describes progress on some supporting activities including the SRI Artificial Intelligence Center Computer Facility, the language QLISP, hardware interface work, and a scanning laser range finder.

Digital data system: User's View of the Network

Abstract: The utilitarian aspect of the Digital Data System is discussed with emphasis on performance objectives that will be important when data communications is inserted into a system of data processing. Objectives for the dependability and quality of data communications are quantified and evaluated in terms of their impact on data processing. Characteristics of the several types of channels available are described in detail along with operational features of particular importance at the interface between data communication and data processing.

Digital terminals for packet broadcasting

Abstract: Roberts illustrated the potential use of packet switching technology by postulating a personal computer terminal using radio broadcasting to connect the user to a computer. The proposed terminal had a unique five-finger keyboard and plasma-discharge display. The keyboard would generate and send characters, one at a time, to the computer using 64 bit packets per character. The computer could convert these to a 35-bit (5X7) pattern and retransmit a 144-bit packet to the terminal to control a 5 X 7 dot matrix character. Thus, the terminal needed no character generation logic and only a minimum of digital control logic to interface keyboard and display to a radio modem. This was a reasonable concept insofar as the terminal was intended to operate within a short distance of the computer to accommodate low-power radios, and so long as only a few terminals were in use.

Computer to tape deck interface

Abstract: An interface for coupling a computer to a plurality of magnetic tape transports, including dual-density transports and combinations of high and low density transports. The interface includes an automatic density selector for detecting the density of data stored on a tape prior to reading and for storing this information for as long as the tape is being used. A read-only memory and other logic circuitry translate computer operating commands into commands readable by a transport formatter. The interface also couples digital data between the computer and the formatter and converts formatter status information into language readable by the computer.

Ignition wave analyzer interface

Abstract: An interface for an ignition coil voltage analyzer is disclosed. The interface includes adaptive sample-and-store logic for secondary peak amplitude detection. The interface also generates timing pulses to effect and facilitate secondary voltage analysis, including frequency component analysis and time domain analysis.

Using large data bases for interactive problem solving

Abstract: Interactive problem solving involves user-machine dialogues to solve unstructured problems, such as selecting marketing strategies and planning mass transit routes. A characteristic of most interactive problem solving systems is that they operate on data bases that are special purpose subsets derived from a large data base. The problem solving system must include code for interfacing with this data base, or the data must be converted to the formats required by the problem solving system. Effective interactive problem solving requires a data management system which provides flexibility in accessing a large data base and fast performance for the problem solving system. This paper describes a method, called data extraction, for interfacing large data bases with interactive problem solving systems. Figure 1 shows the basic components in the interface. A large data base management system is used to maintain and protect a set of data files. Data extraction is used to aggregate and subset from this set to provide information for problem solving. In addition to an I/O interface, data extraction provides interactive data description and presentation functions. For more details on the functional requirements of the data extraction components see [2].

A Fully CAMAC Interfaced Computer Control System for the Vicksi-Accelerators

Abstract: The computer control system for the VICKSI-project uses CAMAC modules as the unique interface. A single loop CAMAC-Serial-Highway will control all the equipment associated with the accelerators and the beam paths. The components of the main-control-console as well as general maintenance-equipment are interfaced to the computer via a Parallel-CAMAC-Highway. No further submultiplexing is done. Special attention was given to the choice and specification of CAMAC-Modules in order to reduce the number of different types and to standardize the ports to the equipment under control. The impact on hardware (cabling, maintenance, error detection) and software design will be reviewed. The software itself is based on the use of a real-time executive in conjunction with an interpreter and a data base allowing a comprehensive addressing scheme and simple system tasks.

Data processing interface system

Abstract: A data processor is coupled with a plurality of peripheral devices via interface units or boxes, each coupled to one or more of such peripheral devices. The data processor and interface boxes are coupled in a full duplex path coupled in a daisy chained or serial manner so that the interface box furthest from the processor along the path has the lowest priority. Data is transferred in cycles with one output word and a priority word being transferred from the processor during each cycle, and with at least one input word capable of being transferred to the processor during each cycle. Apparatus is included to select the interface box with which data transfer is to be made during a cycle, in response to the priority word of the preceding cycle.

The CUPAD System: Real Time Handling of Randomly Acquired Clinical Ultrasound Data

Abstract: The CUPAD system described in the previous paper includes a custom designed hardware interface between a Picker EV-6 Scanner and a Digital Equipment Corporation PDP-15 computer, and a supporting software package. This paper will describe in greater detail the structure and operation of the hardware and the software.

A Computer Architecture for Level Structured Systems

Abstract: The notion of level structured operating systems is receiving growing acceptance in the computing community. These systems are implemented and debugged incrementally, one level at a time. Each level provides a pseudo-machine interface upon which the next level can be implemented. Such systems offer significant advantages from the piont of view of debugging, reliability, understandability, and modifiability over conventionally organized systems. The efficiency price which must be paid for this type of organization can be overcome by providing some simple mechanisms in the hardware to support the level structure. It is the purpose of this paper to point out where the hardware support is needed and to suggest one way of implementing these features.

A Computer Interface for Efficient Zero-Crossing Interval Measurement

Abstract: A technique is described which makes use of a hardware computer interface to efficiently extract zero-crossing interval information from continuous time signals. Each zero-crossing of the input waveform causes the contents of a clock register to be transferred into a clock buffer register simultaneously with the generation of a computer interrupt. Following this, the clock register is restarted and further zero-crossings are prohibited from affecting the device for a set length of time. This length of time is preset to disallow the interruption of the computer until the present zero-crossing interval can be processed. The interrupted computer may read the clock buffer register which represents the elapsed time between the previous two zero-crossings. Since this method results in the measurement of zero-crossing interval information with a minimum computer involvement, a given computer can spend a maximum amount of time processing zero-crossing interval data. An implementation of the technique for use with a PDP-8/L computer is discussed.

Optimum criteria for output interfaces in digital stochastic computers

Abstract: Optimum criteria are discussed for the evaluation of output interface systems in digital stochastic computers. In particular, the ideal probability sensing, device is described, as well as a practical realisation of a variable-accuracy averager.

Digital plotting from a line generator format: an interface

Abstract: A hard copy capability was needed for the CRT of a PDP-11/LDS-2 graphics facility. Available hardware was inconvenient or unsatisfactory for several reasons. An Hewlett-Packard 7210 A Digital Plotter was selected and an interface from standard line generator format to the plotter was designed and built. The results are a fast, quiet, high-quality hard copy capability requiring negligible software.

Initial program loader of basic programs - in working store of computer uses standard control panel interface for read-in

Abstract: The operating panel interface is responsive to a programme switch, and an independent clock system is used. The basic programmes are entered in the working store from a read only memory via an operating panel interface, which simulates the initial programme loading by hand. The use of programmable read only memories allows any number of words of any length to be prepared without requiring a change of the logics. The operation of a key (TUE) resets the flip flop (FF) and one output (Q) is high and the other output (Q) is low. The high signal switches through all AND elements and the clock (T) is released.