Showing papers on "Interface (computing) published in 1977"

Intelligent input-output interface control unit for input-output subsystem

Abstract: An Input-Output Interface Data-Transfer Control Unit, designated as a Line Control Processor, which provides the execution of instructions in accomplish data transfers between a main data processing system and a plurality of different types of peripheral devices. Further, said Line Control Processor provides for the buffering of at least two complete blocks of message data, thus to prevent access errors, since complete record length message transfers can occur in any given data-transfer cycle. The Line Control Processor operates with a standard communications and control discipline which makes the eccentricites of various types of peripheral units transparent to the main system. The Line Control Processor executes data-transfer instructions within the overall system thus relieving the central processor of an involvement in these tasks. Each Line Control Processor handles data-transfer operations with a specific peripheral device and the main system, and also provides "status-count" numbers which provide the main system with information for logically determining the next processing step to accomplish.

Interconnection unit for multiple data processing systems

Abstract: An interconnection unit for connecting multiple data processing systems in a distributed data processing network. The interconnection unit comprises a single controller with control and data sections that connect to each data processing system in the network through an interface circuit and a host processor interface circuit that connects to each data processing system. For one data processing system to transfer information to an other system, the one system requests exclusive control of either the data or control section of the interconnection unit. Each section independently and sequentially tests each interface circuit to determine if a control request exists. When a section grants a request, the requesting data processing system transfers information to or from a memory in that section associated with another system in the network. That memory is accessible to all the data processing systems. The controller sends a signal to the other data processing system to notify it that pertinent information is stored in the memory. The other system then can request control of the interconnection unit and process that information.

Use of Abstract Interfaces in the Development of Software for Embedded Computer Systems

Abstract: : This report describes a procedure for designing computer systems that are developed specifically to be a component of a more complex system. Two significant characteristics of such design problems are the following: the computer system interface is determined by factors outside the control of the computer system designer, and the specifications of that interface are likely to change throughout the life cycle of the system. The purpose of the procedure described in this report is to reduce maintenance costs by means of a software organization that insulates most of the programs from changes in the interface. The procedure is based on the systematic compilation of an assumption list. The assumption list describes those aspects of the interface that future users and other knowledgeable persons consider essential and therefore stable. Other aspects of the interface are ignored. An abstract interface is designed on the basis of this assumption list. A specification of the abstract interface is used to procure the major components of the system. This report explains the principles behind the procedure and illustrates its use. The success of the procedure is primarily limited by the ability of designers and future users to compile an accurate list of assumptions. A side benefit of the procedure is simpler, better structured software. Successful application of the procedure should result in both increased reliability and reduced lift-cycle costs.

Interface system providing interfaces to central processing unit and modular processor-controllers for an input-output subsystem

Abstract: A sub-interface system within an Input-Output Subsystem of a digital data processing system. The interface subsystem comprises a Main System Interface of a central processing unit working with the distribution-control means of a Base Module housing a group of Line Control Processors (individual Intelligent I/O Interface units) dedicated to a specific peripheral device. The Main System Interface is designated as an IOT, or Input-Output Translator, and translates input-output instructions into proper form for delivery to a particular intelligent interface unit which can execute the instructions. The IOT provides a data link identifier to identify each particular data-transfer transaction and receives result information from the Line Control Processor and Base Module to keep the Main System informed of the status or completion of each individual data-transfer operation. The Input-Output Translator provides a selection of priority to be given to competing Line Control Processor requests for access to Main Memory and communicates with individual Line Control Processors in their control of data-transfer operations between various peripheral devices and the Main Memory of the System.

A study in man-machine interaction

Abstract: The performance of users in man-machine interaction (MMI) is described in terms of a number of user- and machine-oriented parameters. The general linear model for experimental design is used as a model of the interaction. Performance measures are selected and a questionnaire developed to gauge user attitudes toward the man-machine system (MMS) and its environment. The interface parameters selected are hypothesized to have a significant effect on the performance and attitude measures.The effects of varying CRT display rates and output delays upon user performance and attitudes in a series of message retrieval tasks were evaluated experimentally. The results support the somewhat surprising conclusion that doubling the display rate from 1200 to 2400 baud produces no significant performance or attitude changes; increasing the variability of the output display rate produces both significantly decreased user performance and a poorer attitude towards system and interactive environment. The generally held notion that increasing output display rates is associated with better user performance is not supported.

Reproduction machine using fiber optics communication system

Abstract: A reproduction machine having a plurality of operating stations and a plurality of devices for controlling operational tasks of said operating stations comprising a master controller having an arithmetic and logic unit for controlling the devices in accordance with sensed operational parameters and a stored operation program and interface means connected in a communication path between the master controller and the devices. The interface means comprises a fiber-optic communication path for isolating the master controller from electrical noise and transients of the devices.

Synchronous microcode generated interface for system of microcoded data processors

Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.

Standard interface files and procedures for reactor physics codes. Version IV

Abstract: Standards, procedures, and recommendations of the Committee on Computer Code Coordination for promoting the exchange of reactor physics codes are updated to Version IV status. Standards and procedures covering general programming, program structure, standard interface files, and file management and handling subroutines are included.

Microcomputer control of machines

Abstract: A microcomputer system is provided that facilitates system interaction with a machine. System architecture provides for processing machine inputs and generating machine outputs under microcomputer program control to enhance capability and flexibility and to reduce special purpose interface circuitry. Use of a microcomputer having an integrated circuit read only memory for program storage, an integrated circuit RAM or scratch pad memory for alterable operand storage, and integrated circuit logic enhances cost, performance, reliability, and other considerations.

Serial data communication system for a reproduction machine

Abstract: A data communication system for an electrophotographic type reproduction machine or copier having a master unit, an interface, and one or more remote units. The master unit includes a programmable controller having a data processor, memory storage for storing programs and command and data bytes, and address and data buses. The interface is connected to the master unit via the address and data buses, and includes a memory connected to the data bus for temporarily storing command and output data bytes from the master unit pending transmittal thereof to the remote units and for storing input data bytes from the remote units pending transfer thereof to the master unit. A first communication path, along which command and data bytes from the interface memory are transmitted to the remote units, couples the interface with the remote units. A second communication path, along which input data bytes from the remote units to the interface memory are transmitted, couples the remote units with the interface.

Microprogrammable control processor for a minicomputer or the like

Abstract: A minicomputer comprises a microprogrammable central processing unit wherein micro-instruction execution speed is optimized through the use of variable micro-instruction timing logic and by grouping micro-instruction according to execution time. Furthermore, data paths are arranged so that micro-routines that implement more complex operations, i.e., memory reference instructions, follow the fastest route possible. When micro-instructions requiring longer data paths are programmed, the computer dynamically varies the length of the microcycle to be a function of both the type of micro-instruction to be executed and the state of the minicomputer when the micro-instruction is to be executed. A microprogrammable processor port is provided to allow coupling of external hardware, e.g., I/O devices, other processors, etc., directly to the microprogrammed control processor. This capability is in addition to the standard input/output system of the minicomputer, thereby providing an alternate interface path for devices requiring very fast transfer rates. These devices interfaced through the microprogrammable processor port are directly coupled to the internal data busses of the minicomputer and addressed under direct microprogram control as if they were internal processor registers. Block transfers of data are provided via this microprogrammable port to allow transfers of large blocks of data without dependence on the I/O system timing of the minicomputer. A remote program load feature is provided whereby an I/O device or data communications interface can initiate a bootstrap operation in a remote computer, i.e., the computer can be halted, a preselected ROM loader program is transfer into memory, all input/output instructions in the loader are automatically configured to the proper select code of the I/O device, and the computer is restarted at the proper loader program starting address.

I/O Terminal identification

Abstract: Control of the data format programmed into an interface means by a computer means is provided in response to the data format required by an I/O device. A register in the interface means is programmed to respond to only a first digital address from the computer means. A switching means having first and second positions is utilized to create "don't care" positions in a digital address from the computer means to the interface means. Because of the "don't care" positions in the digital address the register in the interface means will respond to a second digital address when the switching means is in the first position. The register will not respond to the second digital address when the switching means is in the second position. When the register responds to the second digital address then the computer programs the data format required by a first I/O means into the interface means. When the register does not respond to the second digital address then the computer programs the data format required by a second I/O means into the interface means. Thus, the position of the switching means determines the data format which will be programmed into the interface means.

Bidirectional interface utilizing read-only memory, decoder and multiplexer

Abstract: An apparatus matches control code signals and data signals between data processing units which employ different control code formats. The interface is especially suitable for use between a computer bus interface and a controller or between two separate controllers. It employs read-only memory circuits which convert control code signals from the computer bus into discrete controls and commands compatible with the code format of the controller. The read-only memory circuits are programmable to allow looping programs to be implemented.

Process control system

Abstract: A process control system for multiplex operation of several process control loops. The system includes process input and process output units, analog and computer operation units and operator's interface stations, the exchange of process information between these units and stations being carried out by a time-sharing technique. The system is provided with a first data trunk through which process information through the data trunk is carried out in synchronism with address signals supplied to the address trunk in accordance with a cyclic control routine. Also included is a second data trunk which makes it possible at one's option to modify the cyclic control routine to select a desired mode of operation, the analog and computer operation units and the interface stations signalling whether operation in the manual control, analog control, or control mode is possible. State signals are generated at the operator's interface stations to the respective units to control their signal transmitting or receiving state.

Input/output interface connector circuit for repowering and isolation

Abstract: In a data processing system which includes a base central processing unit, channel, and input/output (I/O) interface to which peripheral devices may be attached, a special attachment is disclosed. The attachment made to the base I/O interface includes connector circuitry which is required when the signals on the input/output interface must be repowered to peripheral devices in an expansion input/output unit, power isolation must be provided between a base data processing system and I/O expansion unit, or a remote peripheral device is to be attached to the base data processing system I/O interface. The connector circuit includes logic which responds to the normal I/O interface signals to energize drivers in the connector circuit to achieve repowering of signals on bidirectional signal lines and unidirectional signal lines.

Memory interface device with processing capability

Abstract: An interface device to provide a data and address path between a data processor, a memory and peripheral devices. The interface device includes an internal arithmetic and logic unit to provide a means for generating and/or modifying addresses for the memory or peripheral devices. The device further includes a plurality of registers for temporarily storing data or addresses as well as information associated with addressing functions, for example, program counter, index register, stack pointer and page addresses. The interface device may be used singly or in combination with like devices as in a slice processing system.

Common polling logic for input/output interrupt or cycle steal data transfer requests

Abstract: COMMON POLLING LOGIC FOR INPUT/OUTPUT INTERRUPT OR CYCLE STEAL DATA TRANSFER REQUESTS Abstract of The Disclosure A data processing system with improved input/output (I/O) techniques is disclosed The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initated interrupt requests to the central processor A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor

CASS: Computer aided schematic system

Abstract: Our interactive system for computer aided editing of schematics (CASS) is described here. The system may be used alone as well as a part of an integrated data-base oriented design environment.In isolated operation, a number of utility programs provide for the use of schematic data in succeeding design phases. As part of an integrated system this schematic data may be stored in, and retrieved from, the data-base directly. Some general aspects of the data-base will be described.Particular attention should be devoted to the very "natural" and powerful user's interface of CASS, utilizing the menu technique on a storage display device, while minimizing the use of kayboard.In order to increase the applicability of the system an intelligent graphic terminal, based on a microcomputer, is under implementation. The configuration of this terminal will be outlined and some of its fundamental design aspects will be described.

An optically isolated digital interface for the SKED system

Abstract: A digital interface to support the SKED software system in recent versions of the PDP-8 computer. One printed circuit card of interface logic and optical isolators can be installed in the OMNIBUS to provide 24 input and 36 output lines to external panels containing input simulation switches and input or output indicators.

1a processor: Control system

Abstract: This article contains a description of the central control, input/output subsystem, processor-peripheral interface, master control console, and the interunit communication bus system. The units are discussed in a manner which highlights comparison of features with No. 1 ess and stresses those features which are most important in meeting the stringent reliability objectives.

Interprocessor communication in systems with distributed control

Abstract: A multiprocessor communication technique, called Sub-Module Interface (SMI) because it enables exchange of information between telephony control units (submodules), was developed for a telephony switching system, thus realizing a distributed control philosophy. In addition to allowing any processor to communicate with any other processor in the system, a variety of devices attached to the SMI can also be accessed by the processors. This paper explains the philosophy and operation of this technique and, based on previous common control concepts in telephony, certain conflicts between these philosophies are noted.

A program system for interactive measurements on digitized cell images.

Abstract: Using a high precision image scanner and a PDP-8/F minicomputer, we have developed a program system for interactive measurements on microscopic images. By giving simple keyboard commands, the operator can run the image scanner and manipulate the digitized images. The interface between the operator and the microscope-computer system is a Tektronix 4010 graphic terminal. The system allows objects to be isolated and parameters to be calculated from each object, e.g., parameters characterizing shape of the object, irregularity in light transmission over the object, area, integrated light transmission, etc. Objects are isolated and parameters are calculated under complete operator control using interactive computer graphics technique. Calculated parameters may be stored in dedicated data records, which are stored in files for later statistical analysis. The system also includes a statistical evaluation part. Technically, the system consists of a command scanner, which translates commands into internal represen...

Automatic microfilm camera operated responsive to data input at a computer terminal

Abstract: An automatic microfilm camera is positioned to take images of a document while it is being read by an operator of a computer terminal. The computer generates a computer index number, and perhaps other significant information, which is forwarded via an interface circuit to display a readout of alpha-numerical images within the photographic area adjacent to the copied document. The camera automatically takes a picture of the document and the display when the operator pushes an "Enter" or other appropriate button on the computer terminal, thereby photocopying both the document and the displayed images. An important aspect of the invention is that the photographic cycle is initiated automatically by an appropriate step in the data entry sequence, whereby the normal data entry procedures are not disturbed by the existance or the use of the camera. An advantage is that the camera and computer are inherently synchronized and cannot lose their mutual sequencing. After developing, the image may be automatically retrieved by the computer and displayed by a suitable microfilm projector.

Data Structure Design

Abstract: Publisher Summary This chapter focuses on data structure design. Many data structures designers realize that data should be specified at two levels: (1) the abstract, user-oriented information structure, and (2) the concrete, machine-oriented storage structure. The design methodology is based on five views of data: (1) data reality, (2) data abstraction, (3) information structure, (4) storage structure, and (5) machine encoding. The design of a data structure should proceed through successive levels, binding only those aspects which are necessary to specify each level. Top management must be able to consider all aspects of data reality. For example, managers in a credit card company care about the availability of plastics for the cards, the appeal of the design of the cards' faces, and other aspects which are probably “irrelevant” in the view of computer personnel dealing with the data. Therefore, such information must be included as a part of the first view of data. Translating an application from the reality into an abstraction is the interface at which data managers decide which aspects of data are relevant to the model—possibly by enumerating the types of queries and updates that may be applied to the data.

Channel control system

Abstract: PURPOSE: To cope with the multiplexing of processings to make processings high- speed by providing an independent control part for every function in respect to a channel in the system equipped with plural channels. CONSTITUTION: Micro program control part 11 controls commands such as I/O start, interrupt and interface between CPU and a channel. Data transfer control part 12 executes data transmission through the data buffer of the channel. Data transfer control part 13 executes the data transmission between the channel and the main memory, the control of indirect data addresses and data chain control. These plural control parts operate independently to be able to cope with the multiplexing of plural channels. Further, these control parts cope with the multiplexing and the complication of processings, as common control parts which operate synchronously with one another, in a high speed by combination of a micro program and hardware. COPYRIGHT: (C)1979,JPO&Japio

Expandable inter-computer communication system

Abstract: This disclosure describes a system for providing a communications channel between a master computer and a plurality of similar or dissimilar slave computers that may be separated by great distances. The foregoing system comprises a buffer unit and at least one computer linkage unit. The buffer unit acts as an interface between the master or control computer, the external hardware that is coupled to the master computer and a plurality of slave computers, and the one or more computer linkage units so that the buffer unit may act as an expandable direct memory access bus to a slave computer and provide communication with a plurality of peripheral systems. The computer linkage unit performs all of the remaining interface functions between the master computer and the plurality of slave computers that are coupled to the master computer. Additional computer linkage units together with additional slave computers may be connected to the original computer linkage unit permitting this system to be easily expandable without extensive modifications.