Showing papers on "Interface (computing) published in 1981"

Numerical control system

Abstract: A numerical control system equipped with a man-machine interface controller (MMC equipment) constructed in the form of a computer. The system comprises an NC unit (11), a programmable machine controller (13) which executes the sequence control relying upon the signals from the NC unit (11) and a machine tool (12), a man-machine interface controller (14) which is equipped at least with a CRT (14d) and a keyboard (14e) and which is constructed in the form of a computer, and a data transmission-reception control unit (15). The data are transmitted and received among the NC unit (11), the programmable machine controller (13) and the man-machine interface controller (14) while they are controlled by the data transmission-reception control unit (15).

Distributed Systems - Architecture and Implementation: An Advanced Course

Abstract: 1. Motivations, objectives and characterization of distributed systems.- 2. Distributed system architecture model.- 3. Interprocess communication layer: Introduction.- 4. Hardware interconnection technology.- 5. Link level.- 6. Hierarchy.- 7. IPC interface and end-to-end (transport) protocol design issues.- 8. Distributed control.- 9. Identifiers (naming) in distributed systems.- 10. Protection.- 11. Atomic transactions.- 12. Synchronization.- 13. Multiple copy update.- 14. Applications and protocols.- 15. Error recovery.- 16. Hardware issues.- 17: Hardware/software relationships in distributed computer systems.- 18. The national software works (NSW).- 19: Ethernet, pup and violet.- 20. Conclusion.- References.

Data encoding for television

Abstract: A transparent data transmission system for encoding data to be transmitted by way of the scan lines of a television video signal, includes interface circuitry for receiving data from a number of input devices each operating at a particular data rate, and encoding processing circuitry which takes the data received by the interface circuitry and arranges it into separate data groups so that each group corresponds to the particular input device which originated the data. The data groups are then inserted, by way of timing circuitry, into corresponding data channels defined in a selected scan line of the video signal. Also, a data channel bit map is defined over a portion of the selected scan line, and data identifying each of the input devices which is providing data to the interface circuitry is inserted into the data channel bit map. Accordingly, when the encoded video signal is decoded to extract the inserted data groups together with the channel bit map, the decoding circuitry can determine, in accordance with the data channel bit map, if a null character contained in the extracted data was provided by an input device to the encoding interface circuitry and, if it was, the decoding circuitry can then allow the null character to be distributed for further processing. The overall transmission system therefore exhibits true transparency.

Digital data processing system having an I/O means using unique address providing and access priority control techniques

Abstract: A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

An experimental study of the human/computer interface

Abstract: An exploratory study was conducted to analyze whether interface and user characteristics affect decision effectiveness and subject behavior in an interactive human/computer problem-solving environment. The dependent variables were performance and the use of the systems options. Two of the independent variables examined, experience and cognitive style, were user characteristics; the other three, dialogue, command, and default types, were interface characteristics. Results indicate that both user and interface characteristics influence the use of the system options and the request for information in the problem-solving task.

Channel interface circuit with high speed data message header field translation and direct memory access

Abstract: The subject channel interface circuit functions in a multiprocessor environment to provide a high speed interface between a processor and the communication channel which interconnects all the processors. The communication channel carries data messages, which messages contain a header field specifying source, destination and control information. The subject channel interface circuit is programmable and serves to dynamically translate the header portion of the data message as it is received and thereby determine whether this data message is to be stored in the processor memory. If the data message is to be stored, the channel interface circuit immediately converts the header field into a hardware address, which is used to activate a specific location in processor memory. The data message is then inputted (via DMA) to this memory location and the appropriate buffer pointers are reset. Thus, the subject channel interface circuit performs all the data receiving tasks, including message storage and linking, without requiring the involvement of the associated processor.

A procedure for designing abstract interfaces for device interface modules

Abstract: This paper describes the abstract interface principle and shows how it can be applied in the design of device interface modules. The purpose of this principle is to reduce maintenance costs for embedded real-time software by facilitating the adaptation of the software to altered hardware interfaces. This principle has been applied in the Naval Research Laboratory's redesign of the flight software for the Navy's A-7 aircraft. This paper discusses a design approach based on the abstract interface principle and presents solutions to interesting problems encountered in the A-7 re-design. The specification document for the A-7 device interface modules is available on request; it provides a fully worked out example of the design approach discussed in this paper.

Mulga — an interactive symbolic layout system for the design of integrated circuits

Abstract: To aid the design of MOS circuits, a suite of programs residing on the UNIX∗ operating system have been designed and written. These programs allow the interactive editing, layout compaction, circuit connectivity extraction, parasitic audit, and timing simulation of MOS ICs within the symbolic domain. The programs make use of an intermediate circuit description language (ICDL), which captures both geometric placement and circuit connectivity. A convenient interface is provided to enable the procedural definition of symbolic layouts in the C programming language. All design may be carried out at a single low-cost work station which incorporates a high-performance color display. In this paper we summarize the operation and use of these programs. In particular, we describe a new compaction algorithm.

Information storage in a decentralized computer system

Abstract: This paper describes an architecture for shared information storage in a decentralized computer system The issues that are addressed include: naming of files and other objects (naming), reliable storage of data (stable storage), coordinated access to shared storage (transactional storage), location of objects (location), use of multiple copies to increase performance, reliability and availability (replication), dynamic modification of object representations (reconfiguration), and storage security and authentication (protection) A complete model of the architecture is presented, which describes the interface to the facilities provided, and describes in detail the proposed mechanisms for implementing them The model presents new approaches to naming, location, replication, reconfiguration, and protection To verify the model, three prototypes were constructed, and experience with these prototypes is discussed The model names objects with variable length byte arrays called references References may contain location information, protection guards, cryptographic keys, and other references In addition, references can be made indirect to delay their binding to a specific object or location The replication mechanism is based on assigning votes to each copy of a replicated object The characteristics of a replicated object can be chosen from a range of possibilities by appropriately choosing its voting configuration Temporary copies can be easily implemented by introducing copies with no votes The reconfiguration mechanism allows the storage that is used to implement an object to change while the system is operating A client need not be aware that an object has been reconfigured The protection mechanism is based on the idea of sealing an object with a key Sealed objects can only be unsealed with an appropriate set of keys Complex protection structures can be created by using such operators as Key-Or and Key-And The protection mechanism can be employed to create popular protection policies such as capabilities, access control lists, and information flow control

Modular instrumentation for monitoring and control of biochemical processes

Abstract: A modular instrumentation system for monitoring and control of biochemical processes, and in particular of fermentation processes is provided. The system includes a plurality of function monitoring and control modules each including a microprocessor and associated memory devices, manual input devices and an interface for the receipt of sensor signals and the transmission of control signals. The modules for a plurality of functions have substantially common design and are adapted for relatively quick conversion to another function. The system may include an instrument console adapted to receive a plurality of the function monitoring and control modules as well as incorporating provision for sensor inputs, power inputs, one or more recorders, one or more pumps and/or an interface for an external computer. The back plane of the console is provided with a conductor array interconnecting the various modules, power supply, pumps, recorders, sensor inputs and external computer interface and incorporates provision for the plug-in connection of the respective modules therewith.

Dedicated microcomputer-based control system for steam turbine-generators

Abstract: A dedicated supervisory control system for a steam turbine-generator comprising a hierarchy of microcomputer subsystems interactive with a conventional analog electrohydraulic control system to provide control and monitoring capabilities during all operating phases of the turbine-generator. The separate microcomputer subsystems are programmed for coordinated interaction and communication through shared, dual-port read/write memory units and each microcomputer subsystem is programmed and configured to handle a separate group of control responsibilities in a distributed control system. The microcomputer hierarchy includes an input and calculations computer having means for interfacing with analog input data sources and sensors which report on various operating parameters of the turbine-generator and from which thermal and mechanical stress and other derived quantities are calculated; a display and communications computer adapted to interface with a plant computer and with an operator control panel and other display and readout devices whereby operating personnel may interact with the control system; and a control computer, standing at the top of the hierarchy, for receiving information from the other computers, for making decisions based on that information and, through input/output ports, for providing the electrohydraulic control system with directions for optimal control of the turbine-generator within its thermal and mechanical limitations. The dedicated supervisory controller provides a plurality of operating modes.

Apparatus for the dynamic in-circuit element-to-element comparison testing of electronic digital circuit elements

Abstract: Apparatus for the dynamic in-circuit testing of digital electronic devices employs a hardware testing circuit that is set by a microcomputer which takes no direct part in the test, so that the test hardware speed is not limited by the computer speed. The apparatus comprises a library of devices equivalent to the devices to be tested, the library including a ROM containing the information regarding the devices needed by the microcomputer for its purpose. An internal interface or router receives signals from the test device that are input signals to its terminals and routes them directly to the corresponding selected device in the library where it becomes an input to that device also. Signals from the test device that are output signals are routed instead to a comparison block where they are compared with the respective output signals from the library reference device. The signals at each corresponding pin of the two devices are compared and upon the presence of a fault the apparatus stops and identifies the pin or pins on which a fault has been detected. An external interface is provided to shift the signal levels as required between the test device and the transistor-transistor logic devices of the apparatus. The signals are sampled during timed periods to account for different propagation times through the apparatus, and different operating speeds of the devices. Provision is made for external or internal clocks, reset and ground connections.

Interface between a processor system and peripheral devices used in a mailing system

Abstract: A peripheral interface board establishes a communications link between a postage value determining system processor associated with a postage scale and a plurality of peripheral devices. The interface includes a microcomputer which receives data and command signals from the system processor. A multiplexer interconnects the peripheral transmit line of the microcomputer with a selected peripheral device, while a further multiplexer interconnects the peripheral receive line of the microcomputer with the selected peripheral device. Typical mailing system peripheral devices include electronic postage meters, an electronic accounting system, a scale computer interface and a printer. In response to command signals from the system processor, the microcomputer establishes a communications link with a selected peripheral device. Communications subroutines include signal transmission and/or receipt, temporary storage of data received for communication to or from a peripheral device and communication with the system processor.

Local network interface with control processor & DMA controller for coupling data processing stations to common serial communications medium

Abstract: A local network interface is used in a network for enabling each of a plurality of data processing stations to communicate with one another via a communications medium. The local network interface is connected between the communications medium and the data processing stations. The local network interface includes a processor, a direct memory access (DMA) controller connected to the processor, means for controlling communications connected between the communications medium and the processor, and memory means which is connected to the processor, to the means for controlling communications, and to the DMA controller. Data residing in the memory means may be accessed for transmission to, and may be updated from, the communications medium via the local network interface.

Optical Information Processing: Fundamentals

Abstract: Basic principles.- Coherent optical processing.- Incoherent optical processing.- Interface devices and memory materials.- Hybrid processors.- Linear space-variant optical data processing.- Nonlinear optical processing.

iMAX: A multiprocessor operating system for an object-based computer

Abstract: The Intel iAPX 432 is an object-based microcomputer which, together with its operating system iMAX, provides a multiprocessor computer system designed around the ideas of data abstraction. iMAX is implemented in Ada and provides, through its interface and facilities, an Ada view of the 432 system. Of paramount concern in this system is the uniformity of approach among the architecture, the operating system, and the language. Some interesting aspects of both the external and internal views of iMAX are discussed to illustrate this uniform approach.

Computer-peripheral interface for a game apparatus

Abstract: A home computer system provides a video processor for use with a television receiver. The video processor can selectively perform a variety of modifications to pixel data under the direction of the CPU of the computer system before the pixel data is stored in a random access memory to effectively increase the speed or data handling power of the system.

A microcomputer system for the control of behavioral experiments.

Abstract: A self-contained microcomputer control system (MCS) is described for controlling and recording events from behavioral experiments using a low-cost microcomputer, the Rockwell AIM 65, and the BASIC language. Features of the system include a printer, alphanumeric display, 4K RAM, 8K BASIC on read only memory (ROM), a cassette interface, a power supply, and a control interface, all contained in a compact enclosure. The control interface allows for 16 inputs and 16 outputs, and includes a real-time clock and versatile machine language subroutines for controlling and recording real-time events. These features make BASIC a suitable user language for this application. The use of this microcomputer control system for operant research in behavioral pharmacology is described.

A translating computer interface for end-user operation of heterogeneous retrieval systems. II. Evaluations

Abstract: The evaluation of the concept of a translating computer interface for simplifying operation of multiple, heterogeneous online bibliographic retrieval systems has been undertaken. An experimental retrieval system, named CONIT, was built and tested under controlled conditions with inexperienced end users. A detailed analysis of the experimental usages showed that users were able to master interface operation sufficiently well to find relevant document references. Success was attributed, in part, to a simple command language, adequate online instruction, and a simplified natural-language, keyword/stem approach to searching. It is concluded that operational interfaces of the type studied can provide for increased usability of existing systems in a cost effective manner, especially for inexperienced end users who cannot easily avail themselves of expert intermediary searchers. Furthermore, more advanced interfaces based on improved instruction and automated search strategy techniques could further enhance retrieval effectiveness for a wide class of users.

Asynchronous interface message transmission using source and receive devices

Abstract: An asynchronous interface enables the transfer of information between a set of devices operating in a loop and having a wide range of operating speeds. Each device can enter a Controller active state in which it sources command frames to control the loop operation. Each device can also enter a Talker active state in which it sources Data frames on a Listener active state in which it received Data frames. The transfer of frames is coordinated by a set of handshakes which enable the frames to be transferred in an asynchronous manner.

Processor implemented communications interface having external clock actuated disabling control

Abstract: An automated mailing system includes a postage value determining system processor, a scale for providing weight indicative signals, a keyboard for operator entry of information relating to a determination of postage, and a plurality of peripheral devices. A peripheral controller interface establishes communications links with the peripheral devices. An incompatible systems interface interconnects a serial communications bus of the system processor and the peripheral controller interface. The incompatible systems interface includes a processor programmed to receive, decode and transmit information from or to the system processor along the serial bus and load or receive information from or to the peripheral controller interface along parallel lines. The communication timing constraints of the serial communications bus for receipt of data signals by the system processor do not permit monitoring of the data transmission by the incompatible systems processor. To accommodate for such timing constraints, system clock pulses of the serial bus are employed at a flip-flop to disable the incompatible systems processor.

Mailing system interface interconnecting incompatible communication systems

Abstract: An automated mailing system includes a postage value determining system processor, a scale for providing weight indicative signals, a keyboard for operator entry of information relating to a determination of postage, and a plurality of peripheral devices. A peripheral controller interface establishes communications links with the peripheral devices. An incompatible systems interface interconnects a serial communications bus of the system processor and the peripheral controller interface. The incompatible systems interface includes a processor programmed to receive, decode and transmit information from or to the system processor along the serial bus and load or receive information from or to the peripheral controller interface along parallel lines. The communication timing constraints of the serial communications bus for receipt of data signals by the system processor do not permit monitoring of the data transmission by the incompatible systems processor. To accommodate for such timing constraints, system clock pulses of the serial bus are employed at a flip-flop to disable the incompatible systems processor.

Document size conversion circuit for a document filing system

Abstract: Picture information stored in a memory device is read out and written into a page buffer and visually displayed on the screen of a CRT display under control of an interface unit for display, through a size conversion circuit.

Computer peripheral testing equipment

Abstract: Equipment for testing computer peripherals is disclosed having a computer, with keyboard and display, for coupling to such peripherals by way of a peripheral connector, the computer being provided with software defining test and exercising routines for operating a peripheral device in a controlled and monitorable manner. The computer has a central processor coupled to a bus system to which is connected a monitor, inter alia defining key functions of the keyboard. The bus system also is connected by way of the peripheral connector to an interface to interface between the computer and various peripheral devices. The computer is a portable microprocessor system provided with plug-in modules containing the software as firmware to define the test and exercising routines required for different peripheral devices. The software defines different peripheral connector configurations applicable to the different peripheral devices concerned and also different key functions for operator control of the test and exercising routines.

Control interface system for use with a memory device executing variable length instructions

Abstract: A control interface system for use with a memory device executing variable length instructions and implementable utilizing integratable field effect semiconductor devices is disclosed. One example of such a system is a speed synthesis device controlled by the central processing unit of a computer. A control latch is utilized to release the control device, such as a central processing unit, after an instruction has been initiated. A plurality of latches, each set by the conclusion of the execution of a previous instruction, are utilized to reset the control latch. An attempted second access of the memory device during the execution of a previous command will result in suspending the operation of the control device until such time as the previous instruction is concluded and the new instruction is initiated.

Method and apparatus for interfacing an electronic scale system with a storage medium

Abstract: An interface apparatus and method are described with which an electronic scale system is connected to a storage medium such as a disk or memory of a data processor and whereby scale transaction data related to the mailing of an article with an electronic scale can be automatically preserved as a unified record along with subsequently appended test information such as an invoice number or customer number. The interface has a programmable memory with which a normal operating mode is provided to enable an operator to conveniently and rapidly store scale transaction data and in response to displayed prompts enter data such as the number of an invoice accompanying the article being mailed. The test data is appended to the scale transaction data so that all of this data can be transmitted as a unified record to a storage medium. The interface is further provided with a supervisory mode with which special examination and service operations can be performed as these are needed for monitoring or corrective steps in case of errors. The interface displays plain language prompts to guide an operator through a normal RUN mode as well as facilitate supervisory and service technician monitoring and control. With an interface of the invention the unified record enables a rapid update of a customer account and shipping information.

Programmable hit matrices used in a hardware monitoring interface unit

Abstract: A hardware monitoring interface unit (HMIU) is coupled to a data processing unit and receives all information transferred between subsystems of the data processing unit. Programmable hit matrices (PHM's) include input latches for receiving the information, memory circuits for storing binary ONE's in locations addressed by predetermined portions of the information and output latches for storing the binary ONE's or "hit" signals read from the memory circuits. The "hit" signals are plug-wired into logic circuits and counters in a monitor to collect statistical data.

An Integrated CAD/Automated Process Planning System

Abstract: In this paper, the integration of an automated process-planning system with an interactive computer graphics system is presented. (The current system is capable of planning hole-making processes.) This paper discusses the graphics system, the generative automated process planning system, their interface and the possibility of interfacing with a larger CAD/CAM system. An example of planning a precision machined part is also presented.

Dynamic subchannel allocation

Abstract: An apparatus for and a method of Dynamic Subchannel Allocation permitting easily field modifiable assignment of Input/Output (I/O) subchannels to I/O channels. Many present day medium-to-large scale computers have an I/O unit(s) with a fixed number of I/O ports or I/O channels for the transmission of information between the computer and peripheral devices. Improvements to these I/O channels, now common in the art, permit multiple peripheral devices to be coupled to the computer through a single I/O channel. Each of these multiple peripheral devices may be said to communicate through an I/O subchannel. A given I/O subchannel designation logically specifies the hardware within the shared I/O channel that is dedicated to communication with the corresponding one of the multiple peripheral devices coupled to that shared I/O channel. The present invention is an improvement which provides for allocation of I/O subchannels to I/O channels in the field rather than at time of manufacture. A random access memory (RAM) is employed which provides the correlation between each I/O subchannel and the I/O channel to which it has been allocated. The RAM is called the Channel Descriptor Stack (CDS). The CDS may be loaded using a variety of techniques. In the preferred embodiment, the CDS is loaded via a specialized processor, called a system support processor (SSP), which also performs those tasks normally associated with system control (e.g., system reconfiguration, interface to the system operator, casualty recovery, etc.).

Mailing system peripheral interface with communications formatting memory

Abstract: An interface between a system processor of an automated mailing system and selected peripheral devices carries peripheral support hardware and software for communication with the peripherals The interface includes a board having a memory wherein programs for formatting communications with the peripherals are stored A working memory for the temporary storage of commands and data for communication to the peripherals and a peripheral controller for establishing a communications link with a selected peripheral are also carried on the interface board The inclusion of additional peripheral devices or the substitution of alternate peripheral devices which would require revision of communications formatting programs does not require reprogramming of the system processor and is accommodated by revising the program stored in the interface program memory