Showing papers on "Inverter published in 1974"

Generalized Techniques of Harmonic Elimination and Voltage Control in Thyristor Inverters: Part II --- Voltage Control Techniques

Abstract: Theoretical techniques of voltage control for the half-bridge and full-bridge inverters are derived based on the results in [1]. Detailed analytical results for the symmetrical pulsewidth modulation method of voltage control are also presented. Voltage control techniques are derived whereby harmonic elimination is possible in variable-frequency variable-voltage three-phase inverter circuits. The technique for the half-bridge inverter is optimized subject to the constraint of switching frequency of the SCR's, using the concepts of modern control theory. Variable-frequency variable-voltage sinusoidal output in three-phase inverters is possible by employing the techniques developed. The methods show great promise in application to variable-speed ac motor drive systems.

Metal base cookware induction heating apparatus having improved power control circuit for insuring safe operation

Abstract: A metal based cookware induction heating apparatus having an improved power supply and control circuit comprised of a chopper inverter including a gate controlled power thyristor coupled to and supplying an induction heating coil with periodic energization currents. A full wave rectifier supplies rectified, unfiltered, unidirectional high voltage excitation potential to the chopper inverter which converts the excitation potential to a comparatively high frequency of the order of 20 kilohertz for supply to the induction heating coil. A gating circuit is provided for driving the chopper inverter directly from the rectified high voltage excitation potential supplied by the rectifier.

Low cast chopper inverter power supply and gating circuit therefor

Abstract: A metal based cookware induction heating apparatus having an improved power supply and control circuit comprised of a chopper inverter including a gate controlled power thyristor coupled to and supplying an induction heating coil with periodic energization currents. A full wave rectifier supplies rectified, unfiltered, unidirectional high voltage excitation potential to the chopper inverter which converts the excitation potential to a comparatively high frequency of the order of 20 kilohertz for supply to the induction heating coil. A gating circuit is provided for driving the chopper inverter directly from the rectified high voltage excitation potential supplied by the rectifier. The gating circuit includes an additional low voltage, direct current excitation potential connected to supply to a timing circuit charging capacitor. A voltage responsive switch such as a SUS or PUT or their equivalents is rendered conductive upon the timing circuit reaching a present value and in turn rendered conductive a constant current high voltage switching transistor connected in series with the primary winding of a pulse transformer across the output of the additional low voltage derived from the main full wave rectifier. The pulse transformer in turn has its secondary winding connected to the control gate of the power thyristor included in the chopper inverter.

Inverter fault protection and frequency limiting circuit

Abstract: An inverter fault protection and frequency limiting circuit for inverters having controlled rectifier and antiparallel diode pairs is described for preventing short circuits of the inverter power supply and for limiting the operating frequency of the inverter. An inhibit circuit is responsive to controlled rectifier forward blocking voltages and antiparallel diode currents to generate a gate inhibit signal for one of the seriescoupled controlled rectifiers when the other one of the controlled rectifiers is not forward blocking or if the time duration of the current through the antiparallel diode thereof is less than a specified controlled rectifier turn-off time. A frequency limiting circuit is responsive to the gate inhibit signal for limiting the maximum operating frequency of the inverter.

Synchronous Motor Drive with Current-Source Inverter

Abstract: Steady-state properties of a variable-speed drive using a synchronous motor fed by a controlled current-source inverter are derived from an equivalent circuit model, including saturation, and are confirmed by experiment. The system is shown to be stable under all operating conditions. Control strategy for open-loop operation is discussed.

Volt-second balancing means for a high frequency switching power supply

Abstract: In order to prevent potentially catastrophic overheating of power switching transistors driving the transformer primary winding in a high frequency inverter power supply, which overheating is a consequence of insidious movement along the B-H curve of the transformer resulting in unbalanced primary winding currents, the currents passing through the switching transistors are differentially compared to develop a signal representative of the imbalance. This error signal is utilized to alter the duty cycle of the drive to one side only of the primary winding. Actual, or tendency toward, core saturation is thereby avoided such that less conservatively rated components may be utilized while failure due to overheating as a result of current imbalance in the inverter transformer primary is avoided.

Regenerative braking circuit

Abstract: An inverter device which delivers a-c power to an induction motor during motoring and receives power therefrom during regenerative braking has a current commutating capability which varies with the input voltage. During the regenerative braking mode of operation, the input voltage is increased by inserting an impedance in series between the d-c power source and the inverter, thereby increasing the input voltage level beyond that of the d-c power source. The resulting increased current commutation capacity and increased voltage provides for greater power generation without increasing the size of the inverter device. During motoring operation the impedance is removed to provide for the free flow of current to the inverter.

Braking effort control

Abstract: During the electric braking of an inverter powered propulsion vehicle, it is desirable that the constant torque performance characteristics be extended to a speed beyond that for which pulse width modulation can be effectively used to control voltage. This extension is accomplished by compensating the current command signal, and thus the motor current, by an amount proportional to the speed of the vehicle and inversely proportional to the inverter d-c voltage during periods of operation above the pulse width modulated speeds. A comparator is provided to select the higher of either the uncompensated or compensated current commands, thereby allowing the current command signal to be unaffected during pulse width modulation modes and to be automatically compensated at speeds thereabove.

Circuits exhibiting hysteresis using transistors of complementary conductivity type

Abstract: The circuits include a complementary inverter, comprised of first and second transistors responsive to an input signal, and means responsive to the input signal, for placing the conduction paths of additional transistors in parallel with the conduction path of the first or the second transistor. The conductivity of the additional transistors is controlled by a feedback signal derived from the output of the inverter. When an inverter transistor is turned on the additional transistors connected across it are also turned on causing the equivalent impedance of the ''''ON'''' portion of the circuit to be much lower than the ''''ON'''' impedance of either one of the inverter transistors.

AC motor control system

Abstract: A control system for an A.C. motor which is connected to the output terminals of a thyristor inverter, a capacitor is connected between the D.C. input terminals of the thyristor inverter, and the respective thyristors constituting the inverter are extinguished by self commutation due to an oscillating current produced by the capacitance of the capacitor and the reactance component of the armature coils of the A.C. motor connected to the A.C. output terminals of the thyristor inverter, and a current in the waveform of pulses produced by electric oscillation is delivered in a predetermined phase sequence to the armature coils of the A.C. motor.

Emergency lighting system with high efficiency inverter

Abstract: An emergency lighting system utilizes a high efficiency tuned inverter to energize a fluorescent lamp upon the dropping of the AC line voltage below a predetermined value. The inverter includes a pair of transistors controlled by an IC controller to be switched alternately at zero collector voltage thereby to operate in a low loss switching mode. A first transformer couples the inverter with the fluorescent lamp, and together with a ballast capacitor and a capacitor across the primary winding, sets the operating frequency. An auxiliary winding on the first transformer provides timing information to the IC to cause the transistors to switch in step with that frequency. High efficiency switching is achieved by making the transistor base drive proportional to transistor collector current. A feedback transformer having a pair of windings coupled with the respective transistor collectors serves this function, these windings being magnetically coupled with an input winding which in turn feeds a current to the IC. The IC controller performs a plurality of functions and includes a zero-crossing detector for receiving the feedback current and a pair of output drivers for the respective transistors. Also included in the IC controller is a low battery inhibit circuit and an AC voltage inhibit circuit. Outputs from these inhibit circuits are combined in a logic circuit serving to energize the inverter when battery voltage is above a specified value and AC line voltage is below a specified value and to disable the inverter when either the battery voltage is below a specified value or the AC line voltage is above a specified level.

MOSFET bistrap buffer

Abstract: A bootstrap inverter is cascaded with a bootstrapping push-pull amplifier through a MOSFET, interconnecting particularly the output mode of the inverter with one input node of the push-pull amplifier, the output nodes of both amplifiers swing between ground and Vg, the input node of the push-pull stage swings between near ground and a voltage larger than Vg. The MOSFETs in the amplifiers have capacitive source-to-gate coupling for bootstrap action and conduction at below saturation current levels in the steady state. Two such buffer circuits can be combined to establish a two phase, buffered clock.

Harmonic Analysis of a Synchronized Pulse-Width-Modulated Three-Phase Inverter

Abstract: In pulsewidth-modulated inverters used for variable-frequency applications, a number of harmonic control policies can be used. Most of these policies are complex to implement by hardware. The most simple and yet effective technique is synchronizing or the synchronized harmonic control policy. This paper uses double Fourier analysis techniques to obtain the output harmonics as a function of pulsewidth, pulsing frequency, and output frequency. The method obtains the harmonics as analytical functions and thus provides the necessary relationships for control studies and system optimization. The more significant theoretical results are provided and theoretical and experimental results obtained from a 25-kW three-phase pulsewidth-modulated inverter, are compared.

Induction cooking unit having all pan safe operation, wide range power control and low start-up and shut-down transients

Abstract: An induction heating unit including inverter circuit means comprised by a gate controlled thyristor and commutation circuit coupled together in circuit relationship and excited from a set of power supply terminals connected to a source of excitation potential. An induction heating coil is coupled to and excited by the inverter circuit means in a manner such that the loading on the induction heating coil determines at least in part the operating frequency at which the inverter circuit means operates. Gating circuit means comprised by a gating signal generator and enabling circuit means are coupled to and control turn-on of the gate control thyristor with the gating circuit means comprising a feedback sensing circuit coupled to the induction heating coil for deriving a feedback trigger signal synchronized with the frequency of operation of the commutation circuit.

DC-voltage supply means for an inverter

Abstract: A control circuit for controlling a supply of D.C. voltage to the input of an inverter. The circuit includes a control arrangement and apparatus for adjusting the D.C. voltage supply in accordance with signals applied to the control arrangement. The circuit also includes a current sensor for sensing the current supplied to the inverter, a sensing device for an A.C. voltage component connected across the input to the inverter, and apparatus for applying signals to the control arrangement in accordance with the current sensed by the sensor and the A.C. voltage component sensed by the sensing device.

The development of a gate assisted turn-off thyristor for use in high frequency applications

Abstract: The development of a. high power, high frequency, inverter thyristor is described. The techniques and procedures used to achieve forward blocking recovery times of less than 2 microseconds are summarized, and electrical test data are included to show that other thyristor Parameters are not too adversely impaired.

Induction cooking appliance having improved protection circuits

Abstract: An induction cooking appliance for heating a metallic utensil by means of an ultrasonic frequency magnetic field. The appliance includes a smooth, substantially non-metallic cooktop for supporting the utensil, and a work coil mounted below the cooktop for coupling the magnetic field to the utensil. The work coil is arranged in a solid state inverter circuit, including a gate controlled thyristor and a commutating capacitor, arranged to convert a d.c. voltage to current pulses of ultrasonic frequency. Simplified inverter protection circuits assure that conditions within the inverter do not exceed the component ratings. The protection circuits include a load sensing circuit for disabling the inverter when unloaded or when improperly loaded. An associated circuit responds to the power operating level of the inverter for varying the sensitivity of the load sensing circuit. Further protection is provided by an over-voltage limit circuit also adapted to disable the inverter. Means are provided for limiting potentially damaging voltage transients which may be generated when the inverter is disabled by the load sensing circuit. User convenience is enhanced by providing, in combination with the on/off inverter operation, a pilot light circuit which operates from a low voltage supply but responds to a small portion of the energy tapped from the inverter ciruit so as to be illuminated only when the inverter is actually operating.

Voltage level conversion circuit

Abstract: An interface circuit utilizing bipolar and complementary field effect transistors for interfacing low voltage circuits with higher voltage circuits. The circuit input at the lower voltage level comprises a bipolar transistor connected as an emitter follower. The circuit output is a FET inverter having its input connected to the collector of the bipolar transistor. A divertable current sink in the form of a third FET is connected in series with the inverter and to the emitter of the bipolar transistor.

Short HVDC transmission system with power factor control

Abstract: A method and apparatus for regulation of the power factor of a 3-phase network fed with power from another 3-phase network via a short high-voltage direct current transmission link interconnecting the two networks. The d.c. transmission link includes rectifier and inverter stations connected at opposite ends of the link and the inverter station is controlled in such manner as to supply power to the fed network at a variable leading power factor in dependence upon the actual power factor of the fed network.

Control process for operating a parallel-resonant circuit inverter that supplies an inductive charge, as well as the parallel-resonant circuit inverter operated by this method

Abstract: An improved parallel-resonant circuit inverter of the type having a rectifier, a thyristor DC/AC converter connected thereto and operating at a controllable frequency, a parallel resonant circuit with an inductive load and a method of operation of such circuit whereby the converter voltage U is maintained at a constant operating value UB for a constant DC current Ig = Igo, in a first control range characterized by a low resonant-circuit damping, and control of the direct current Ig for the purpose of maintaining the DC/AC voltage constant at its operating value UB, in the case of a constant thyristor extinction time tL = tLO, in a second control range characterized by a high damping, as well as by transition from the first to the second control range, if tL becomes equal to tLO in the case of increasing resonant-circuit damping, and transition from the second to the first control range, if Ig become equal to Igo in the case of decreasing damping.

Voltage-Fed High-Frequency Bridge Inverter Circuit

Abstract: A bridge inverter circuit with series tuned load is analyzed. The criterion for triggering frequency range is derived. Design considerations for the SCR and the tuning capacitor ratings are discussed.

Generation of gate pulses for control of PWM thyristor inverter

Abstract: A set of timed gate pulse series for control of a PWM thyristor inverter is generated through the steps of generating three phased series of triangular waveform signals the repetition frequencies of which are proportional to the level of an input command and have a ratio therebetween of 4:2:1, level-comparing the three series of triangular waveform signals with the input command and, on the basis of crossover points therebetween, generating three series of pulses having a pulse width ratio therebetween of 1:2:4, selecting one of the three series of the generated pulses depending upon the level of the input command, and converting the selected series of pulses to a set of desired timed gate pulse series for control of the PWM thyristor inverter.

Direct current to alternating current electronic inverter with overload and short-circuit protection circuitry

Abstract: A high-efficiency, low-cost D.C. to A.C. electronic inverter generates sinusoidal ouptut voltage(s) by utilization of an oscillator and divider circuitry that generates extremely precise symmetrical control signals. These control signals cause a push-pull amplifier comprising power switch drive transistors to periodically alternately energize power switches comprising two banks of matched output transistors, that in turn generate high current inputs to a ferro-resonant transformer. The transformer is tuned to provide the desired output sinusoidal voltage. The inverter incorporates unique overload and short-circuit protection electronics that prevent catastrophic destruction of the power switch drive transistors as well as the power switch transistors. Furthermore, to maximize the inverter's efficiency, the power switch driving circuit receives electrical energy from the ferro-resonant transformer in order to insure deep saturation of the power switch transistors. In addition, the push-pull amplifier incorporates further electronics for preventing driving of the power switch drive transistors during failure in the oscillator or divider circuitry.

Method and apparatus for operating an inverter consisting of two sub-inverters

Abstract: An improved method and apparatus for operating an inverter comprising two sub-inverters having their outputs connected with each other through a choke with a center tap in which the outputs are controlled such that two AC output voltages displaced in phase with respect to each other are applied to the choke. According to the present invention in order to minimize the voltage-time area at the choke, the two AC voltages are reversed in polarity within the range of the control angle at least once with reversals in the two voltages always taking place at the same time and in opposite directions.

Symmetric output, digital by three counter

Abstract: A digital divide by three ( divided by 3) counter providing a symmetrical square wave output waveform from a square wave input signal utilizing digital logic devices. The circuitry includes a conventional divide by three digital counter whose nonsymmetrical square wave output is fed to one input of an AND gate and to one input of a delay type flip-flop circuit after being fed through a logic inverter. The square wave input fed to the counter is additionally fed to the other input of the AND gate and the delay type flip-flop, whereupon the output of the AND gate and flip-flop are fed to an OR gate whose output comprises the desired symmetrical waveform.

High-output solid state dc-ac inverter with improved overload protection and control logic circuitry

Abstract: A DC-to-AC inverter is disclosed utilizing a clock oscillator and an amplifying circuit for delivering AC power at a relatively high output level. A protection circuit is provided to sense potentially damaging transient signals, isolate them from the amplifier circuitry, and return most of the power of the transient signals to the DC supply to both conserve power and protect the solid state circuitry. The output transistors are biased such that, as the collector current approaches a predetermined maximum current level, the base-emitter bias voltage of the transistor approaches the maximum amplitude of the applied base drive signal, to limit the collector current which in turn limits the AC output current of the inverter under short circuit conditions. An amplitude sensing circuit measures the output level of the inverter and disables the inverter whenever the AC output or the DC supply voltage goes below a predetermined level. A standby power circuit maintains normal operation of the oscillator and control logic during temporary interruptions or reductions in the DC supply.

Inverter adaptive lock-out technique

Abstract: An impulse commutated inverter is provided with control apparatus for firing a first commutating rectifier, sensing the subsequent flow of capacitor overcharge current in a parallel reset resistor and delaying a fixed time interval after current flow is first sensed before an opposite serially connected commutating rectifier is permitted to fire. The inverter is thus allowed to generate minimum pulse widths to achieve the maximum possible output voltage in pulse width modulation operation without increasing the risk of shoot-through resulting from simultaneous conduction of the two commutating rectifiers.

Scr inverter systems

Abstract: An A.C. to D.C. to A.C. inverter system including a current controlling element connected between a source of D.C. voltage and an SCR inverter is described. The current controlling element, responsive to various circuit parameters, such as load current, power or instantaneous SCR voltage, maintains the circuit parameters within safe limits. Current controlling elements such as transistors, SCR's, thermistors, pressure sensitive resistors and other current controlling devices are described.

Set-preferring R-S flip-flop circuit

Abstract: A set-preferring R-S flip-flop circuit comprises a first inverter circuit and a second inverter circuit The first inverter circuit includes first, third and fifth MISFETs of a first conductivity type channel and second, fourth and sixth MISFETs of a second conductivity type channel The first and third MISFETs are connected in parallel with each other and are connected between an output terminal of the first inverter circuit and a first power source terminal in series with the fifth MISFET The sixth MISFET is connected between the output terminal and a second power source terminal, and the second and fourth MISFETs are connected between the output terminal and the second power source terminal in series with each other The second inverter circuit includes a seventh MISFET of the first conductivity type channel connected between an output terminal of the second inverter circuit and the first power source terminal, and an eighth MISFET of the second conductivity type channel connected between the output terminal and the second power source terminal An output signal of the first inverter circuit is transferred to input electrodes of the seventh and eighth MISFETs An output signal of the second inverter circuit is fed back to input electrodes of the first and second MISFETs A reset signal is applied to input electrodes of the third and fourth MISFETs A set signal is applied to input electrodes of the fifth and sixth MISFETs

Apparatus for generating three phase sinusoidal voltages

Abstract: Apparatus for inverting input DC source voltage to generate three-phase, sine-wave, line-to-line output voltages. A first inverter produces three-phase, flat-top, full-wave voltages in relation to a point of reference potential on three-phase output conductors and a second inverter operating in synchronism with the first inverter generates a single-phase, flat-top voltage at three times the frequency of the output of the first inverter. A transformer having a plurality of voltage taps is coupled between the point of reference potential and the second inverter. First and second banks of voltage level selector controlled rectifiers are coupled to the voltage taps and are selectively gated to produce alternate pairs of stepped ascending and descending voltages which are selectively coupled to the three phase output conductors by voltage distributors to complement the three-phase, flat-top, full-wave voltages to complete the line-to-neutral, three-phase waveforms. These waveforms combine to form threephase, line-to-line voltages. The voltage level selector controlled rectifiers which are commutated naturally during generation of the stepped voltages are coupled directly to the voltage distributors and the voltage level selector controlled rectifiers which require auxiliary commutation are coupled to the voltage distributors through commutating switches. Current flow through the commutating switches is reduced by capacitors coupled across the three-phase output conductors to provide for a leading load power factor. The capacitor values may be selected so as to reduce the current through the commutating switches to zero for all expected load conditions to thereby allow the elimination of the commutating switches and the level selector controlled rectifiers coupled thereto.