Showing papers on "Inverter published in 1981"

A New Neutral-Point-Clamped PWM Inverter

Abstract: A new neutral-point-clamped pulsewidth modulation (PWM) inverter composed of main switching devices which operate as switches for PWM and auxiliary switching devices to clamp the output terminal potential to the neutral point potential has been developed. This inverter output contains less harmonic content as compared with that of a conventional type. Two inverters are compared analytically and experimentally. In addition, a new PWM technique suitable for an ac drive system is applied to this inverter. The neutral-point-clamped PWM inverter adopting the new PWM technique shows an excellent drive system efficiency, including motor efficiency, and is appropriate for a wide-range variable-speed drive system.

Apparatus and method for providing a logical exclusive OR/exclusive NOR function

Abstract: Circuits are illustrated using CMOS design techniques for incorporating N and P channel transistors into a circuit to obtain the functions of exclusive OR and exclusive NOR signal generation. This is accomplished by utilizing a given logic value signal as a control signal to pass the other input signal for three of the four possible logic value conditions. The fourth condition must generate the output signal from a selected one of the input signals, through the use of an inverter.

The Delta Modulation Technique in Static PWM Inverters

Abstract: Pulsewidth modulation (PWM) techniques are employed in voltage-source inverters to produce a variable output voltage containing the least possible harmonic distortion over a wide frequency range. To achieve these objectives, compromises are made in terms of control circuit complexity, smoothness of inverter operation, and overall system reliability. The delta modulation (DM) technique fulfills the aforementioned performance requirements with a minimum of circuit complexity, smooth inverter operation and with improved system reliability.

New Static VAR Control Using Forced-Commutated Inverters

Abstract: This paper describes the system outline and the operating results of a new type of 20MVA Static VAR Generator (SVG), which is already in operation in electric power field since January of 1980. This SVG consists of force-commutated inverters of the voltage source and can be operated in both, inductive and capacitive modes, by simple control of the output voltage of the inverter. Special emphasis is placed on the system outline, electrical designing features and the operating results which coincide with the theoretical analysis.

Controlling method for inverter

Abstract: PURPOSE:To eliminate irregular rotation and unstability at a low speed by constantly controlling a DC voltage in PWM mode in low speed range of several 10% of speed at several 10% and controlling it in PAM mode over several 10%. CONSTITUTION:A PWM modulator 17 controls PWM according to a command value S3 with the reference output S1 of a speed reference circuit 15 being 0-30%, thereby controlling an inverter transistor 5 ON or OFF by a base drive circuit 16. The output S5 of the modulator 17 becomes constant value between 30 and 100% of the reference output S1, instead a voltage pattern generator 13 outputs as a command value an output S2 proportional to the reference output S1, controls a voltage control circuit 11 in response to the output the difference from the DC voltage detected by a DC voltage sensor 12, thereby controlling the DC output voltage of a thyristor 2 equal to the command value V1.

Inverter drive for switched reluctance motor: circuits and component ratings

Abstract: A variable speed drive using a switched-reluctance motor permits a simpler and cheaper inverter than a PWM inverter for an induction motor. The various inverter circuit options are considered for singlewinding and bifilar-wound motors, noting the advantages of the bifilar 4-phase arrangement from the inverter's viewpoint. The inverter design process for a traction drive with a 3:1 constant power range is explained, followed by the calculation of main and commutation component ratings. Experimental results are given for chopping and for two single-pulse speeds. The control electronics are briefly described.

Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator

Abstract: A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.

Pulse width modulation inverter with battery charger

Abstract: An inverter is connected between a source of DC power and a three-phase AC induction motor, and a microprocessor-based circuit controls the inverter using pulse width modulation techniques. In the disclosed method of pulse width modulation, both edges of each pulse of a carrier pulse train are equally modulated by a time proportional to sin θ, where θ is the angular displacement of the pulse center at the motor stator frequency from a fixed reference point on the carrier waveform. The carrier waveform frequency is a multiple of the motor stator frequency. The modulated pulse train is then applied to each of the motor phase inputs with respective phase shifts of 120° at the stator frequency. Switching control commands for electronic switches in the inverter are stored in a random access memory (RAM) and the locations of the RAM are successively read out in a cyclic manner, each bit of a given RAM location controlling a respective phase input of the motor. The DC power source preferably comprises rechargeable batteries and all but one of the electronic switches in the inverter can be disabled, the remaining electronic switch being part of a "flyback" DC-DC converter circuit for recharging the battery.

High efficiency turn-off loss reduction network with active discharge of storage capacitor

Abstract: A turn-off loss reduction network is applied to the power transistors of a double-ended inverter circuit to reduce power dissipation therein. A switched resonance discharge circuit is utilized to discharge the storage capacitor of the turn-off loss reduction network. Dissipation during discharge is eliminated by including an energy recovery circuit in the discharge network which is operative to return the energy to the input voltage source of the inverter. The gate discharge circuit includes a gated resonant discharge path with an inductive storage medium having a secondary winding or otherwise coupled to return the energy to the input voltage source. At the beginning of the conduction cycle of the power switching transistor, a gate is enabled which allows the capacitor to discharge into the inductive storage medium. When the discharge current reaches its peak value, the gate is disabled, and the energy stored in the inductive medium is discharged to the source by flyback action.

Three-phase inverter arrangement

Abstract: An inverter arrangement for generating a three-phase AC output voltage is provided with three pulse-controlled, free-running single-phase inverters. The inverters are connected at their inputs to a DC voltage source, and at their outputs to respective low-pass filters. The low-pass filters are connected to corresponding single-phase transformers, each having an output winding. The output windings of the single-phase transformers are connected to one another in a Y-circuit configuration to produce the output AC voltages, having a grounded neutral terminal. Each of the single-phase inverters is controlled by an associated pulse control device which contains a vector-oriented control device and a control unit. A vector oscillator generates signals corresponding to a symmetrical three-phase system of reference vectors for the vector-oriented control devices.

Transistor inverter device

Abstract: Base current is supplied from a base driving circuit (27) to bases of paired inverter transistors (14, 15) through a transistor (36), and an inverter circuit (11) oscillates at a rated output. When the operation of an electric discharge lamp (20) becomes abnormal, an IC-ed control circuit (49) is rendered operative responsive to output of an abnormality detecting circuit (51) to turn the transistor (36) ON and a transistor (48) OFF, and the operation of inverter circuit (11) is thus stopped. A capacitor (33) in an auxiliary power source (38) is charged by output of the base driving circuit (27) and the control circuit (49) is driven responsive to output of auxiliary power source (38) when the inverter circuit (11) is left inoperative.

Current overload protection for inverter of uninterruptible power supply system

Abstract: Current overload protection is provided for an inverter of an uninterruptible power supply system; a shutdown circuit responds when a current overload is present, and a plurality of at least three comparators having different input threshold and different time delays at their respective outputs operate such that when an extreme overload occurs, the inverter will be shut down immediately, whereas it will be shut down after predetermined longer periods with correspondingly lesser amounts of current overload present.

Fast switching field effect transistor driver circuit

Abstract: A high frequency inverter power supply having isolation between the drive circuitry and the Power Switching device and utilizing a Field Effect Transistor as the Power Switching device is described. Circuitry for rapidly charging the gate capacitance of the Field Effect Transistor for enhancing the rate of its switching to the conductive state and for rapidly discharging the gate capacitance for enhancing the rate of its switching to the non-conductive state is shown.

A high-speed monolithic InP MISFET integrated logic inverter

Abstract: High dynamic range monolithic n-channel InP MISFET integrated inverter circuits with delay times of 350 ps have been fabricated on Fe-doped semi-insulating substrates using ion implantation for channel and contact regions and pyrolytic SiO 2 for the gate insulation. These circuits, consisting of two active elements, a 4-µm channel-length normally-off enhancement driver MISFET, and a 4-µm gate-length normally-on depletion load MISFET are designed for use in direct-coupled high-speed logic. In comparison to the dominant GaAs MESFET approach, the present circuit does not require level shifting and uses only a single power supply. With V_{DD} = 12.4 V these inverters exhibit logic swings of 11.2 V, noise margins of 4.5 and 3.2 V, and dc gain in the linear region of 3.1.

Power-on reset circuit

Abstract: A power-on reset circuit in which a first CMOS inverter drives a second CMOS inverter to turn on a third and fourth CMOS inverter. A reset pulse results at the output of the fourth inverter while the third inverter holds a first MOSFET in an off condition and a capacitor is charged through a resistive network comprised of two MOSFETs. When the capacitor is charged past the switching point of the first inverter, the POR pulse is terminated and the first MOSFET is turned on, allowing the capacitor to be charged to the point that no static current flows through the reset circuit because no static current flows through the first inverter.

d.c. To d.c. voltage regulator having an input protection circuit, a d.c. to d.c. inverter, a saturable reactor regulator, and main and auxiliary rectifying and filtering circuits

Abstract: A multiple output d.c. to d.c. regulating circuit including an input protection circuit for providing protection against input overcurrent, input transient voltages, sustained input overvoltage and input polarity reversal. The protection circuit powers a d.c. to a.c. inverter which generates high frequency square-wave signals. The square-wave signals are fed to a magnetic saturable reactor regulator which has its controlled windings connected by a rectifying filtering network to a pair of main output terminals and connected by transformer rectifier filter circuits to a plurality of auxiliary output terminals. The d.c. output voltage across the main output terminals is sampled and is compared to a reference voltage of an integrated circuit operational amplifier. The output of the integrated circuit operational amplifier is connected to the control winding of the saturable reactor for controlling the controlled windings so that the square-wave signals are pulse width modulated to regulate the d.c. voltages developed across the pair of main output terminals and the plurality of auxiliary output terminals. A soft starting circuit prevents high in-rushing currents from damaging the d.c. to a.c. inverter. An overload protection circuit senses overloads on the input and main output terminals and causes removal of power from the regulating circuit.

Time-varying feedback gains for power circuits with active waveshaping

Abstract: This paper presents a line interfaced inverter that employs a dc-dc converter to actively shape its ac current waveform. The duty cycle applied to this converter to control the current is determined in a closed loop fashion. The incremental dynamic response of the power circuit is found to be highly dependent on the ac voltage and current waveforms and therefore varies on a 60 Hz basis. With fixed feedback gains this variance would give closed loop poles that moved during the cycle. To avoid the problems that a time-varying system response would cause, a novel control scheme is proposed. This scheme uses periodically varying feedback gains to counteract the power circuit's time dependent response in a way that gives closed loop poles that do not move. Results of a Parity Simulation are included to verify the validity of this approach.

Microcomputer-based pulse width modulated inverter fed machine drive system

Abstract: Regulation of inverter-machine drive system torque and frequency in accordance with operator commands is achieved by the use of an improved, microcomputer-based, control apparatus. At machine frequencies less than a preselected machine frequency, inverter pulse width modulation signal pulses and half cycle polarity signal pulses are supplied by the control apparatus to the inverter to regulate the duration and conduction sequence, respectively, of inverter switching devices in accordance with pulse width modulation signal data computed by equilateral triangulation and stored half cycle polarity signal data. At frequencies above the preselected machine frequency, when computation of inverter pulse width modulation signal data becomes impractical, inverter pulse width modulation signal pulses are synthesized from stored data. This achieves simplification of control hardware and provides improved machine drive system performance.

A high density CMOS inverter with stacked transistors

Abstract: This paper describes a complete CMOS inverter, whose P-channel transistor is made from laser annealed polycrystalline silicon and is superimposed upon the N-channel transistor. The single gate is common to both transistors. The process is NMOS compatible and polysilicon transistors with channel lengths down to 4 micrometers have been made.

Apparatus for controlling a PWM inverter-permanent magnet synchronous motor drive

Abstract: Apparatus for controlling a permanent magnet AC synchronous motor supplied by a forced commutated inverter that does not use a mechanical shaft position sensor. A control loop regulates an inverter frequency and maintains inverter synchronism with the motor using electrical angle feedback signals developed from measured flux signals that have been phase shifted.

A current sourced inverter with saturating output transformer

Abstract: A current sourced inverter with saturating output transformer offers advantages where a DC converter must regulate an isolated output voltage over a 10 to 1 range of input voltage in a dense package capable of 300 watt output.

Technique for pulse dropping in pulse-width modulated inverters

Abstract: The maximum output voltage obtainable from a pulse-width modulated inverter is less than that obtained when the inverter output waveform is a square wave of wanted frequency. Therefore, in order to realise the full potential of the inverter it is necessary to make the transition from a PWM output waveform to a square wave. Due to the practical limitations of the power circuit, it is not possible to reduce the width of unwanted pulses in the PWM waveform gradually to zero, but instead, pulses of a finite width must be dropped abruptly from the waveform. This results in step changes in the output voltage which can produce large current transients in the power circuit and the load. It is shown that the traditional method of pulse dropping is unsatisfactory and a new method is proposed which produces much smaller step changes in output voltage.

Automatic fault protection system for power recovery control

Abstract: An adjustable speed pumping system includes a plurality of pumps respectively driven by variable speed A.C. motors each having a power recovery circuit. Each power recovery circuit includes a series connected rectifier bridge, an inductive reactor and an inverter coupled to the secondary winding of the motor which has an A.C. source connected to the primary winding. A fault clearing mechanism is included in each circuit and includes solid state switches in the bridge actuated by a current level sensor coupled to the inverter output. The power recovery circuit also includes current foldback circuitry and secondary gating circuitry coupled to thyristors in the inverter. The power recovery circuits can be connected in parallel with a single motor and the system includes circuitry for sensing the highest amplitude current in the parallel circuits and controlling all circuits with this current. Each pump has a valve associated with the outlet and circuitry associated therewith to operate the pump at a low forward speed upon receipt of a stop command until the valve is closed to prevent significant reverse flow through the pump.

Self generative variable speed induction motor drive

Abstract: An inverter controls an induction motor in response to signals from a power factor control circuit. The power factor control circuit receives signals related to motor terminal voltages and multiplexes them to a comparator. The inverter and multiplexor are sequenced each time the comparator input reaches a reference level. The frequency of the inverter is thus self generated. The power factor of the system can be controlled to implement a variety of control strategies.

Low power CMOS frequency divider

Abstract: Means are described for generating a pair of oscillator signals that will respectively drive P and N channel transistors in Class B. These signals are used to clock a synchronous inverter stage that will only change state during the appropriate time interval. Pairs of such stages are cascaded using common clocking to create a shift register which drives an output inverter, the output of which is coupled back to the input of the register. The output stage also has series-coupled P and N-channel transistor pairs for each pair of clocked inverters. Each transistor pair has its gates driven by the respective pair of clocked inverters. The output stage switches at a frequency which is a submultiple of the oscillator frequency, with the submultiple being equal to the number of inverters minus one. Since the inverters are fully Class B there is no direct current conduction due to simultaneous transistor conduction. The clock input capacitance of the shift register becomes part of the oscillator turning capacitance and thus requires no power dissipation. Furthermore, since the inverters switch at a submultiple of the oscillator frequency, output capacitance charging and discharging power is made negligible.

TTL to CMOS Interface circuit

Abstract: An interface circuit including a FET inverter with its N channel device being part of the controlled leg of a first current mirror and its P channel device being part of the controlled leg of a second current mirror. The operating point of the inverter is the reference signal applied on the input to the current mirrors. The controlled leg of the first current mirror includes a variable current source responsive to the input signal and the controlled leg of the second current mirror includes a variable current sink for improving the response time of the inverter and compensates the inverter for manufacturing tolerances.

A design of CMOS polycell for LSI circuits

Abstract: We have designed CMOS polycells with a uniform height for LSI random logic circuits. The design objective was to minimize the product of propagation delay and chip area while allowing noise margins to be at least 25 percent of V_{dd} . Designable parameters were identified to be channel widths in p -type and n -type transistors. Analytical models were derived to show the existence of an optimal solution point. Physical interpretations of models were also given. SPICE was used to simulate propagation delays and noise margins in inverter (INR), 2- and 3-input NAND and NOR gates under worst-case conditions. The chip performance of polycell-based CMOS circuits was then estimated by averaging performances of these five logic gates. With 3.5-{\mu}m design rules, the channel widths in p -channel and n -channel transistors were designed to be 35{\mu}m and 17{\mu}m , respectively.

Harmonic distortion in single-channel MOS integrated circuits

Abstract: Expressions assuming a simple square-law MOSFET model are presented for the low-frequency harmonic distortion of an enhancement-mode source follower. These theoretical results are compared to measurements of several integrated versions of the three circuit types. For a given fabrication process, the main factors determining the amount of distortion for all three circuits are the quiescent output voltage and the output swing; to a first order, the distortion does not depend on bias current or device geometries. The distortion of an enhancement-mode source follower has a similar behavior to that of an enhancement-load inverter with the same output quiescent voltage and output swing; both distortions are nearly proportional to the body-effect coefficient. For the same output quiescent voltage and output swing, the distortion of the depletion-load inverter is the highest among the three circuits, but is practically independent of process parameters.

Flux feedback firing control for a load commutated inverter

Abstract: A load commutated inverter synchronous motor drive system wherein a thyristor firing control of the inverter is determined by the amplitude of pesudo flux waveforms which are derived from the integral of the line voltages coupling the inverter to the motor being driven. A firing strategy is provided based on the premise that optimum thyristor firing in a load commutated inverter operating at a leading power factor occurs at a point just below the peak of the forthcoming pseudo flux waveform which point comprises an amount of volt-seconds necessary to effect current commutation plus a nominal safety margin. The determination and control is implemented, preferably, in a software phase lock loop but can, when desirable, be implemented in hardware.

Inverter-type power supply circuit for electrical machining

Abstract: An inverter-type power supply circuit for electrical machining comprising a plurality of AD-DC-HF-DC (PULSE) inverters jointly connected between a common source of commercial alternating current and a single electrical machining gap. A common pulsing means is provided for the individual switches in these plural inverter circuits for providing thereto in unison a succession of time-spaced groups (Ton, Toff) of elementary signal pulses to provide across said gap concurrent occurring channels of time-spaced groups (Ton, Toff) of elementary machining pulses (τon, τoff) which channels are superimposed upon one another across the machining gap. The plural inverter circuits include individual high-frequency transformers each of which, or a portion of which, has a plurality of settings for transforming the original voltage to a desired output voltage level which settings are selectively established to selectively establish the desired voltage and current characteristics of the superimposed elementary machining pulses in time-spaced groups.