Showing papers on "Inverter published in 1984"

Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits

Abstract: A simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits. A detailed discussion of this short-circuit dissipation is given based on the behavior of the inverter when loaded with different capacitances. It was found that if each inverter of a string is designed in such a way that the input and output rise and fall times are equal, the short-circuit dissipation will be much less than the dynamic dissipation (<20%). This result has been applied to a practical design of a CMOS driving circuit (buffer), which is commonly built up of a string of inverters. An expression has also been derived for a tapering factor between two successive inverters of such a string to minimize parasitic power dissipation. Finally, it is concluded that optimization in terms of power dissipation leads to a better overall performance (in terms of speed, power, and area) than is possible by minimization of the propagation delay.

Cascode voltage switch logic: A differential CMOS logic family

Abstract: A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

The Use of Harmonic Distortion to Increase the Output Voltage of a Three-Phase PWM Inverter

Abstract: By adding a measure of third harmonic to the output of each phase of a three-phase inverter, it is possible to obtain a line-to-line output voltage that is 15 percent greater than that obtainable when pure sinusoidal modulation is employed. The line-to-line voltage is undistorted. The method permits the inverter to deliver an output voltage approximately equal to the voltage of the ac supply to the inverter. Thus an induction motor of standard rating with respect to the ac supply to the inverter can deliver very nearly full power at rated speed when supplied from the inverter. This is achieved without pulse dropping or any other form of mode-changing.

A Comparative Investigation of a Three-Phase Induction Machine Drive with a Component Minimized Voltage-Fed Inverter under Different Control Options

Abstract: Possibilities for minimizing component cost in variable- speed drives with frequency control by solid-state converter are investigated. It is shown that in a three-phase system voltage and frequency control of a three-phase squirrel-cage machine may be attained by PWM of the output of a simplified bridge inverter with only four switches. As the phase voltages are in principle asymmetrical, this technique is called phase asymmetric PWM (PAPWM). The operational region of PAPWM control is investigated theoretically in the frequency plane, compared to PWM control of a six-element bridge, and shown to have application possibilities. The system was experimentally tested on a 1O-kVA four-transistor inverter and experimentally compared to the operation of a six-transistor inverter of the same rating. The entire signal electronics subsystem was also minimized regarding components by using a specially dedicated IC circuit developed for PWM applications in three-phase systems. These results prove that a PAPWM system with a B4 bridge can be operated to give the same operational drive characteristics as a B6 bridge with PWM. The price to be paid for using a bridge with only four switches lies in the higher pulse frequencies required to give the PAPWM the same characteristics as a conventional system. Since transistor switches may be operated at high switching frequencies with low switching losses, the system is well suited to transistor inverter control of induction machine drives.

Instantaneous Feedback Controlled PWM Inverter with Adaptive Hysteresis

Abstract: A new control strategy for a PWM inverter controlled through adaptive hysteresis in an instantaneous feedback loop is theoretically analyzed and verified through simulations and a low-power experimental circuit. This control gives excellent performance under various load conditions, and it is especially effective in reducing load injected harmonics.

Modulation of the Chopping Frequency in DC Choppers and PWM Inverters Having Current-Hysteresis Controllers

Abstract: In a dc chopper converter having its load current regulated by a feedback controller of the fixed hysteresis type, the chopping frequency is shown to depend on the square of the counter EMF of the load. In a pulsewidth modulated (PWM) inverter, the counter EMF is modulated at the output frequency, so the chopping frequency is modulated at twice the output frequency. For a three-phase PWM inverter feeding a three-wire load, the chopping frequency modulation is not smooth. This is explained to be a consequence of the fact that the three phase currents must sum to zero, rendering one of the three current controllers redundant.

Control system for a voltage-type inverter

Abstract: In a control system for a voltage-type inverter which comprises a bridge connection of electric valves each comprising a reverse parallel connection of a semiconductor switching element and a diode, and converts a DC power to an AC power by means of PWM control, a voltage detection device is provided to detect an output voltage of the inverter. A voltage correction circuits corrects the pulse width of the pulse width modulation signal in accordance with the comparison of the detected voltage and the PWM signal. A drive circuit, which provides a dead time during which the switching elements of the electric valves connected in series with each other are concurrently non-conductive, uses the corrected PWM signal for driving the switching element.

Method and system for reconnecting inverter to rotating motors

Abstract: When an inverter (10), is disconnected from a rotating motor (10A) due to power failure or motor accident, it is necessary to connect the inverter power again to the motor rotating by the inertia force in order to keep the motor rotating. To achieve the above reconnection, the inverter is controlled in accordance with open-loop control method, without use of any motor speed detecting means, thus improving control response speed. In reconnection, the inverter is started at a frequency higher than the rotating motor speed and at a voltage lower than the rated value; when a predetermined time has elapsed after the starting voltage was applied to the motor, only the frequency is decreased; when inverter driving current drops below a predetermined value, the frequency is held and only the voltage is increased until the voltage-to-frequency ratio reaches a predetermined value.

Modified current source inverter fed induction motor drive with reduced torque pulsations

Abstract: A new technique for reducing the torque pulsations in a conventional current source inverter fed induction motor drive is presented. This does not attempt to improve the current waveforms, but modifies the airgap MMF directly. This is based on the use of a motor with two sets of balanced phase windings, with a 30 electrical degree phase difference between them, and each set being fed from a conventional current source inverter. The two inverters are further connected in series so that they can operate from the same current source. As a consequence of this arrangement, the voltage rating of the components of each inverter is reduced, along with reduced torque ripple. This scheme has been experimentally verified and compared with the performance of a conventional scheme.

Simulation study of DC transit systems with inverting substations

Abstract: The increasing use of chopper-controlled regeneratively braked stock in rapid transit and suburban railways has brought into focus the problems of limited energy receptivity in the DC supply network. While the use of on-board rheostatic braking or mechanical braking are established methods of dealing with non-receptivity, an alternative arrangement using inverting equipment at the DC substation has been introduced at some locations in Japan, Germany and Brazil. This paper describes a simulation-based study of a rapid-transit system with substation inverters, which was undertaken to establish operating limits and optimum design criteria which could be generally applicable. The paper deals with the choice of installed inverter capacity, inverter location, current commutation limits and inverter control. In addition the energy-saving consequences of using inverter equipment are discussed in detail. The implications of fitting inverters, with respect to the bulk AC supply system, in terms of voltage distortion, voltage regulation and reactive power demand, are considered for a range of typical values of short-circuit level.

Inverter-drive controlling apparatus

Abstract: In a controlling apparatus for a simulated sinusoidal wave of unequal width PWM inverter, wherein PWM signal comprises a data region and a HALT region in each of carrier period timer, the carrier period timer T 0 and data unit timer T 2 are controlled by each other independent digital values by each other independent microcomputers (5, 6) or by use of each other different timers (10, 11), and the data unit timer T 2 is controlled by an output of a power source voltage fluctuation detector (18), thereby to provide a constant voltage-frequency characteristic even at voltage fluctuation.

Controller for providing PWM drive to an A.C. motor

Abstract: A controller for providing PWM drive to an inductive load incorporating an input rectifier bridge (24) the output of which is filtered by capacitors (106, 108) and which includes input impedance (116, 118) for limiting start-up current surges. A by-pass network (124) controlled from a high voltage sensor circuit (32) controls the by-pass network. The sensor circuit also provides an enablement signal (40) to a pulse width modulation circuit (42). A low voltage power supply (36) is coupled with the output (26) of the rectifier and filter function (24) to supply isolated power to the discrete driver networks of a driver circuit (48). The driver networks are controlled from the pulse width modulation circuit which, in turn, is controlled from a microprocessor (68). The drivers provide drive to three, phase designated transistor pairs of an inverter switching bridge (50) which is supplied power from the rectifier and filter circuit (24).

Uninterruptible ac power supply

Abstract: An uninterruptible ac power supply permits parallel operation between a commercial ac line and an inverter unit, greatly simplifies the monitoring of the commercial ac line and minimizes the transient of output voltage during the switching of mode. The uninterruptible ac power supply is comprised of an iron core divided with magnetic shunts into three sections and has an output winding, a winding for a commercial ac line and a winding for an inverter unit, one each wound on the aforementioned three sections of the iron core, the said three windings so disposed that the output winding is wound on one terminal section and the windings for the commercial ac line and the inverter unit are wound on the remaining two sections.

Solid-state inverter including a multiple core transformer

Abstract: A D.C. to A.C. inverter using switching transistors driving a multiple-core transformer which includes a high-permeability saturable core upon which both the primary and secondary windings are wound and one or more lower permeability non-saturating cores upon which the primary and/or secondary windings are wound to provide additional self-inductance. The inverter switching transistors drive the two halves of the transformer's center-tapped primary winding on alternate half-cycles under the control of a feedback winding which is wound on the saturable core. A non-saturating core about which the primary winding is wound, and a capacitor connected in parallel with both halves of the primary winding, protects the switching transistors against transients, prevents the saturating core from going into hard saturation, and efficiently transfers energy stored in the leakage inductance of the primary winding from half-cycle to half-cycle. A second non-saturating core about which the secondary winding is wound contributes additional self-inductance to the output circuit to limit output currents to a safe value, allowing the inverter to be operated safely with short-circuited output terminals or an electron discharge lamp, which exhibits dynamic negative resistance. Control windings on the two non-saturating cores and serially connected with a variable impedance are used to control and/or regulate the magnitude of electrical energy delivered to the load. The multicore transformer is assembled by means of bobbin wound primary and secondary windings through which the center leg of ferrite E-core shapes may be inserted to provide the desired saturating and non-saturating flux paths.

Ac uninterruptible power system

Abstract: A system to provide substantially uninterruptible AC power. Line voltage is applied to a load through a solid state electronic switch. A squarewave inverter powered by batteries in connected across the load. When line power is reduced to a predetermined level, the switch opens disconnecting the line, and after a short time delay of less than a millisecond, the inverter starts. Upon restoration of normal line power, the process is reversed; the inverter stops and after a like short time delay, the switch closes reconnecting the line.

Method and apparatus for fault time operating of an elevator _

Abstract: An elevator drive motor 1 is normally energized from an AC power source 8 via an AC-DC converter 4 and a DC-AC inverter 3. When the power source fails the elevator is braked and the inverter is supplied from an emergency battery 11 to access the nearest floor for passenger discharge. If a fault occurs in the inverter it is disconnected from the motor by opening a switch contact 15a, and the closing of a further contact 15b enables the converter to energize the motor in a "reverse function" mode from the battery.

Refrigerator control system

Abstract: A novel refrigerator control system is disclosed which comprises an inverter for driving a motor for a compressor, and a change-over device for driving the compressor directly with a commercial power supply when the compressor motor is not driven by the inverter.

CMOS substrate bias generator

Abstract: A generator for producing a negative bias voltage on a semiconductor device employs an on-chip oscillator driving two charge pump circuits. The oscillator produces a frequency inversely related to the negative bias, using a feedback circuit, thus reducing standby current. Each of the charge pumps include a CMOS inverter for controlling the transistor that functions as a diode connection to the ground terminal, producing an efficient charge transfer and speeding up generation of the bias voltage. Both charge pumps are used during power-up so the bias is rapidly increased to the operating level, then one is turned off to reduce current drain. A shunt circuit prevents CMOS latch-up during power-UP by coupling the substrate node to ground, preventing forward bias of N+ source/drain regions with respect to P substrate.

Parallel-resonant bridge-inverter fluorescent lamp ballast

Abstract: Center-tapped DC power to a self-oscillating full-bridge inverter-type fluorescent lamp ballast is obtained from a regular power line by way of a voltage doubler. The DC power is supplied to the inverter through an inductor means having two separate windings on a common magnetic core--with one winding being positioned in each leg of the DC power supply. The full-bridge inverter, which comprises four switching transistors connected in usual full-bridge fashion, comprises a center-tapped parallel-tuned L-C circuit connected across its AC output, thereby providing a center-tapped sinusoidal voltage to its load, which consists of a fluorescent lamp connected in series with a current-limiting capacitor. Due to the effect of the inductor means, the current provided to the bridge is substantially constant during a complete period of the inverter's oscillation. The arrangement is symmetrical and provides for the center-tap of the DC voltage source to be at the same potential as the center-tap of the inverter's AC output; which means that the center-tap of this inverter or ballast output may be grounded without the need for using an isolation transformer.

Design concepts and force generation in inverter-fed synchronous machines with permanent magnet excitation

Abstract: Synchronous machines with permanent magnet excitation can be designed for high power densities and low losses. This paper initially provides an overview of various machine concepts. Constructions with flux concentration and others with air gap oriented magnets are described. A comparison provides dimensioning rules for designs with minimal amounts of permanent magnetic material. On the basis of this, measures are outlined which improve the thrust density and further reduce the losses. These are: 1. design of machine and current inverter with more than three independent phases to achieve a square wave shape for the field and current; 2. employment of appropriately laminated poles to reduce the armature reaction in conjunction with measures which increase flux concentration. The effectiveness of these measures is demonstrated with the use of an example. For a current loading of 100 kA/m, a mean force density of 100 kN/m2is attainable. In conclusion, a machine concept is described which allows control of the exciter field from the armature, thus enabling a more flexible adaptation to the drive requirements.

D-Latch circuit using CMOS transistors

Abstract: A latch circuit includes a CMOS inverter to which a logic signal is applied to the input through an input terminal, which inverter continues to supply an output signal to its output terminal; and first depletion type p and n-channel MOS transistors connected in series to each other, with the CMOS inverter being interposed therebetween. The latch circuit further includes second depletion type n and p-channel MOS transistors which are supplied, at their gates, with an output signal from the CMOS inverter; the second n-channel MOS transistor being connected between the first p-channel MOS transistor and a power supply terminal, and the second p-channel MOS transistor being connected between the first n-channel MOS transistor and a ground.

Inverter control system for providing an easily filtered output.

Abstract: An inverter control system for selecting an angle set defining an inverter output waveform in response to various operating conditions of the inverter (10). The inverter control system selects an angle set in response to signals representing the power factor () of the load and the normalized DC bus voltage (PU VDC) to minimize the harmonic content of the inverter output waveform and to compensate for voltage drops occuring between the DC power supply and the load. The inverter control system is also responsive to the inverter filter output current (IO) to detect fault conditions and in response thereto, to select at least one angle set defining a waveform to reduce the voltage at the load to zero while allowing the filter output current to increase to a given percentage of the rated current.

Feasibility of DC Transmission with Forced communication to Remote Loads

Abstract: Previous researchers have analysed the forced commutated HVDC inverter and have concluded that it could be used to meet the reactive power at the inverter terminals. This investigation is a further technical appraisal involving a two terminal transmission scheme to a remote load with no ac generation at the load. Several possible inverter configurations are discussed.

Self-alignment processed amorphous silicon ring oscillators

Abstract: Amorphous silicon field-effect transistors (a-Si FET's) have been integrated into eleven-stage ring oscillators. The inverter consists of an n-channel driver a-Si FET and an n+ a-Si load resistor. a-Si FET's were fabricated by the self-alignment process. Ring oscillators with a gate length of 5 µm and a gate width of 120 µm achieved a propagation delay time of 210 ns, the lowest reported to date. Those with a length and width of 5 and 1200 µm, respectively, achieved 540 ns. These propagation delay times are about two orders of magnitude faster than those attained previously.

CMOS latch cell including five transistors, and static flip-flops employing the cell

Abstract: A five-transistor CMOS static latch cell (80) useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node (IN), a data storage node (82), a complementary data output node (94), a clock input node (CLK) for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter (N96, P98) has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET (N96) and a P-channel IGFET (P98). The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes (108, 110) are connected to the data storage node (82). A cross-coupled switching element comprising a second P-channel IGFET (P116) has its gate connected to the complementary data output node and is arranged to selectively connect the data storage node (94) to the voltage supply node. A third P-channel IGFET (P115) has its channel arranged to selectively connect the data storage node to the voltage supply node when cell is disabled. A second N-channel IGFET (N126) is arranged to selectively connect the data storage node (82) to the data input node. A high impedance leakage current discharge path (126) electrically connects the data storage node to the one voltage supply node, and discharges any leakage current on the data storage node. The high impedance leakage current discharge path may take a variety of forms, and need not comprise a discrete resistor.

Induction heating cooking device

Abstract: PROBLEM TO BE SOLVED: To provide an induction heating cooking device which can control accurately an induction heating means based on the true temperature of a cooking vessel by suppressing the influence of induction heating to a temperature detector. SOLUTION: The outputs of three temperature detectors 18-20 are given to a controller 35. The controller 35 supplies a high frequency current to an induction heating coil 3 through an inverter circuit 36. A current transformer 44 is inserted to the output side of the inverter circuit 36. The secondary side output voltage of the current transformer 44 is given to the controller 35 through an inverter current detector 45. The controller 35 corrects the detected temperatures of the temperature detectors 18-20 according to the inverter current value given from the inverter current detector 45. COPYRIGHT: (C)2006,JPO&NCIPI

Driving large capacitance in MOS LIS systems

Abstract: The effect of two factors on the delay of a driver chain were analyzed. The first factor is nonzero delay of an unloaded inverter. Computer simulation shows that considerable savings in area and speed can be achieved. The second factor is the difference between propagation delay time and rinse time. Simulation showed that only a slight improvement in speed might be expected by optimizing this difference.

Electrical Characteristics of Large-Scale Integration Silicon MOSFET's at Very High Temperatures,Part III: Modeling and Circuit Behavior

Abstract: The effects of high temperature (27°C to 300°C) on electrical characteristics of long n and p channel metal-oxide semiconductor fieldeffect transistors (MOSFET's) are used to extend the validity of the conventional (room temperature) large and small signal models of these devices. A complementary metal-oxide semiconductor (CMOS) inverter's transfer characteristics and switching speed performance, and the frequency response of a simple resistive load inverter are presented, with temperature as a parameter. Some implications of the models developed, on analog MOS circuit design (for high-temperature, operation), are discussed.