Showing papers on "Inverter published in 1992"

Investigation of fault modes of voltage-fed inverter system for induction motor drive

Abstract: The reliability of power electronics systems is of paramount importance in industrial, commercial, aerospace, and military applications. The knowledge about the fault mode behavior of a converter system is extremely important from the standpoint of improved system design, protection, and fault tolerant control. This paper describes a systematic investigation into the various fault modes of a voltage-fed PWM inverter system for induction motor drives. After identifying all the fault modes, a preliminary mathematical analysis has been made for the key fault types, namely, input supply single line to ground fault, rectifier diode short circuit, inverter transistor base drive open, and inverter transistor short-circuit conditions. The predicted fault performances are then substantiated by simulation study. The study has been used to determine stresses in power circuit components and to evaluate satisfactory post-fault steady-state operating regions. The results are equally useful for better protection system design and easy fault diagnosis. They will be used to improve system reliability by using fault tolerant control. >

Novel approach to high speed CMOS current comparators

Abstract: A novel high speed CMOS integrated current comparator structure is presented which uses a source-follower input stage and a CMOS inverter as a positive feedback. It exhibits short propagation delay and occupies a small chip area.

On continuous control of PWM inverters in the overmodulation range including the six-step mode

Abstract: The power output and the dynamic performance of pulse width modulation (PWM)-controlled AC motor drives can be improved by increasing the inverter output voltage through overmodulation. Two different solutions are proposed to increase the output voltage in a continuously controllable fashion up to the maximum possible value, which is reached in the six-step mode. The solutions differ in their approach. A space vector strategy is used for high dynamics performance high switching frequency drives, while a field-oriented PWM method is used for low switching frequency high power inverters. The methods are described and analyzed, and experimental results are presented. >

Leakage current reduction for a high-frequency carrier inverter feeding an induction motor

Abstract: A PWM inverter with an induction motor often has a problem with a leakage current that flows through the distributed electrostatic capacitance from the motor windings to the ground. The authors present an analytical model of the system with leakage current and the strategy to suppress it. Two types of suppression circuit are discussed. The current-type circuit, although compact in size, not only acts as an excellent suppressor but also becomes a high-performance filter of the output voltage. >

Active filtering of harmonic currents in three-phase, four-wire systems with three-phase and single-phase nonlinear loads

Abstract: A novel active harmonic-neutralizing filter is proposed which eliminates current harmonic effects, caused by any configuration of nonlinear loads in a three-phase, four-wire systems. The authors present proposed filter topologies and simulation results verifying the concept. Theoretical analysis of the circuit is included to facilitate a detailed converter design. The proposed topology is shown to have distinct advantages over traditional approaches to the problem, particularly over the three single-phase inverter approach. >

Apparatus and method for dynamic voltage restoration of utility distribution networks

Abstract: A system and method is provided compensating utility distribution line transients such as voltage sags in a dynamic manner, by inserting a voltage signal in series with the distribution signal having a magnitude and phase to effectively cancel out the voltage deviation caused by a network disturbance. An energy storage device such as a storage capacitor is used to provide energy to an inverter circuit which is controlled to generate the series-inserted signal. Preferably a converter such as a chopper is utilized between the storage element and the inverter, to provide a constant dc input to the inverter. A controller generates a corrective error signal based upon the deviation between the utility supply voltage as affected by the disturbance, and the nominal ideal voltage signal, and adjusts the insertion voltage so as to optimize real power delivery to the utility distribution line.

Switching frequency optimal PWM control of a three-level inverter

Abstract: A pulse-width modulation (PWM) method for the control of a three-level inverter is described. Switching frequency optimal-PWM method (SF0-PWM) works with a constant carrier frequency not synchronized with fundamental stator frequency. SF0-PWM gives an optimal utilization of mean thyristor switching frequency permitted, therefore PWM carrier frequency may be chosen to a value of two times the permitted mean thyristor switching frequency. The signal processing structure is simple. Many applications of three-level- inverters work with a dc-link neutral point not stabilized from the power input converter

Switching frequency optimal PWM control of a three-level inverter

Abstract: A pulse-width-modulation (PWM) method for the control of a three-level inverter is described. The switching frequency optimal-PWM method (SFO-PWM) works with a constant carrier frequency not synchronized with fundamental stator frequency. SFO-PWM gives an optimal utilization of the mean thyristor switching frequency permitted; therefore, PWM carrier frequency may be chosen to a value of two times the permitted mean thyristor switching frequency. The signal processing structure is simple. Many applications of three-level inverter work with a DC-link neutral point not stabilized from the power input converter. A neutral-point potential control is described, which is capable of stabilizing potential by varying the switching sequences of the three-level inverter itself. Results from computer simulation and practical experience show the good performance of SFO-PWM. >

Electrostatic discharge protection circuit for integrated circuits

Abstract: An ESD protection circuit that uses the well-known SCR latchup effect present in CMOS processes to divert the ESD current pulse away from sensitive circuit structures. The circuit uses an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latchup. This feature enables the SCR to absorb a high current pulse on the CMOS pad structures caused by an ESD event, while also preventing the circuit from latching when an ordinary CMOS voltage is applied to the pad while the circuit being protected is unpowered. The circuit insures that the SCR will latch independent of breakdown effects, while also allowing the threshold voltage at which latchup occurs to be adjusted into the circuit by varying the sizes of two FETS used as the voltage divider.

DC/AC inverter controller for solar cell, including maximum power point tracking function

Abstract: A DC/AC inverter controlling system controls a DC/AC inverter so as to continuously output maximum AC power thereof, taking account of solar energy generated from a solar cell. The DC/AC inverter controlling system comprises: a DC/AC inverter unit for inverting DC (direct current) power derived from the solar cell power source into AC (alternating current) power to be supplied to an AC power line; a power variation judging unit for judging whether or not a variation measured during a predetermined time period and occurring in the AC power outputted from the DC/AC inverter unit, exceeds a predetermined value, thereby producing a power variation judging signal; and a power controlling unit for controlling the DC/AC inverter unit so as to reduce the power variation to substantially zero in response to the power variation judging signal, while the power variation does not exceed the predetermined value. As a result, the AC power outputted from the DC/AC inverter unit becomes a maximum value thereof.

Analysis and design of a series voltage unbalance compensator based on a three-phase VSI operating with unbalanced switching functions

Abstract: Voltage unbalance in AC supply systems is typically corrected by means of a shunt connected thyristor-controlled static VAr compensator. This approach has the disadvantage of slow response, harmonic injection into the AC system, and the requirement for large passive components. The proposed system consists of a three-phase PWM voltage source inverter, connected in series with the line through a three-phase transformer. The unbalance compensation is achieved by canceling the negative sequence component of the line-to-line voltages of the source. It is also shown that by having the inverter operate with unbalanced switching functions, it is possible to balance the load voltage and to control the amplitude of the positive sequence component in order to perform load voltage regulation. A complete mathematical description of the method is presented, demonstrating that the compensation can be achieved with low kVA inverters and low harmonic injection. Implementation procedures, design equations, and a design example are also included in order to illustrate the proposed method. Experimental results of a 1.5 kVA laboratory prototype system confirm the feasibility of the technique. >

Current sharing control in a parallel inverter system

Abstract: This inverter system is directed to an inverter system in which a plurality of inverters adapted for generating output voltages corresponding to a voltage reference and a frequency reference respectively given through voltage controllers and frequency controllers are operated in parallel. In this inverter system, a difference between an output current of a corresponding inverter and output currents of other inverters is detected. By implementing the d-q axis orthogonal coordinate transform processing to that current difference, a first correction signal relating to the frequency of an output voltage of that inverter and a second correction signal relating to the amplitude of the output voltage thereof are provided.

A rule-based fuzzy logic controller for a PWM inverter in photo-voltaic energy conversion scheme

Abstract: A rule-based controller based on fuzzy set theory for controlling the output power of a pulse width modulation (PWM) inverter in a photovoltaic (PV) energy conversion interface scheme is presented. The objective is to track and extract the maximum available solar power from the PV array under varying solar insolation levels. To achieve this the power error and the rate of change of this error are used as input signals to the fuzzy rule-based controller and its output signal is used to control the PWM inverter. The input error signals are fuzzified and expressed as linguistic labels characterized by their membership grades. Using a fuzzy relation matrix, a set of 49 rules find fuzzy logic operations, the controller output is obtained. The fuzzy controller output expressed in linguistic labels is defuzzified to obtain the actual analog signal to control the PWM inverter. The proposed fuzzy rule-based controller is simulated and experimentally verified, and is found to give good power tracking performance. >

Class-D zero-voltage-switching inverter with only one shunt capacitor

Abstract: A class-D zero-voltage-switching (also called soft-switching) inverter with only one capacitor in parallel with either transistor, along with an approximate analysis and experimental results, is introduced. The inverter offers both zero turn-on and zero turn-off switching losses, yielding high efficiency at high frequencies. In addition, soft switching reduces switching noise associated with the high-frequency ringing at the switching instants. The transistor voltage stresses are low, similar to those in conventional class-D and pulse-width-modulated inverters. This permits the use of low-on-resistance MOSFETs, reducing the conduction losses. A 50 W class-D inverter was built and tested. The theoretical and experimental results were in good agreement. The inverter combines, low transistor peak voltages and low conduction losses, as in PWM converters, with low switching losses and low noise as in single-ended resonant convertors.

Space-vector PWM voltage control with optimized switching strategy

Abstract: Since space vector modulation offers superior performance with respect to other modulation techniques, it is important to establish the sequencing strategy which is best suited for variable-frequency AC drives. The characteristics of regular direct-direct (DD) and inverted direct-inverse (DI) sequencing strategies are investigated both analytically and experimentally. The two strategies are compared with respect to the current ripple, the current spectrum, and the commutation losses. It was found that DD sequence offers superior performance for the majority of loads, such as induction motor drives. For other types of inverter loads, with small or leading power factors, the optimal modulation strategy consists in using the DI sequence when the output voltage is low and the DD sequence if the modulation index is between m(M) and 1. For best results, the switch-over point M has to be evaluated as a function of load and inverter design. >

Voltage compensating CMOS input buffer

Abstract: The CMOS voltage compensating input buffer circuit of the present invention provides a means to stabilize input level trip points and is comprised of a voltage compensating circuit having an input node and an output drive node coupled to an input buffer. The voltage compensating circuit receives its input from a voltage adjusting circuit that follows changes in V CC while its output drive node is coupled to the series connected CMOS input buffer circuit having an input node and an output node. The buffer's input node receives a signal that VIH/VIL trip points will determine if the output is to be a high or a low and the buffer's output node then couples the resultant level to an output buffer circuit comprised of a CMOS inverter which provides the final output drive. The present invention provides trip point levels corresponding to industry standard VIH/VIL levels to accurately determine the corresponding output with operating voltage supplies (regulated or unregulated) operating between 2 V to 7.5 V.

Energy control circuit for a thermal inkjet printhead

Abstract: A circuit (10) for controlling the energy delivered to a heater resistor (RH) of a thermal inkjet printhead. The circuit includes a decoder (12) for receiving an address for the heater resistor in a multiplexed environment. When the heater resistor is addressed, the output of the decoder is level shifted through a pair of inverters (24, 26) and transmitted to the gate of a PMOS driver (34) that delivers the energy to the heater resistor (RH). The PMOS driver (34) responds to the voltage level of the adjacent inverter output in setting the level of the driver output voltage that is applied to the resistor (RH). Feedback circuitry in the form of an analog (32) or digital (42) comparator compares the driver output voltage (VOUT) against a reference voltage (VREF). The comparator's output signal is fed back through the level shifter (16) as the inverter output that is applied to the gate of the PMOS driver (34). The inverter output adjusts the driver output voltage so as to maintain the voltage (Vo) across the heater resistor at a level that delivers a desired amount of energy to the heater resistor (RH).

Multiple frequency ring oscillator

Abstract: A multiple frequency oscillator responds to a control signal to selectively produce an output signal having a first frequency or a second frequency. The oscillator includes a plurality of inverter stages (481 -485) with the input of each inverter stage coupled to the output of another inverter stage. At least one of the inverter stages includes first and second transistors (50,51) having current paths connected in parallel, a third transistor (52) having a current path connected in series with the current paths of the first and second transistors (50, 51) between a first voltage source (Vdd) and the inverter stage output, and a fourth transistor (53) having a current path connected between the inverter stage output and a second voltage source (Vss). The control electrodes of the first, third, and fourth transistors (50, 52, 53) are connected to the input of the inverter stage. A control signal controls the conductivity of the second transistor (51) to select the frequency of output signal of the oscillator (44).

Sensorless speed detection of inverter fed induction motors using rotor slot harmonics and fast Fourier transform

Abstract: A novel approach to sensorless speed detection for adjustable-speed AC drives is described. No a priori knowledge is required about the motor construction, electrical parameters, or load condition. In addition, no external tuning is needed for the system. The technique is based on instantaneous spectral estimation using the fast Fourier transform, whereby the speed-dependent slot ripple harmonic frequency is determined. For the assessment of this technique, an all-digital speed detector has been built around a general-purpose 386 microcomputer. The performance of this detector over a wide range of inverter frequencies and load conditions is discussed. >

Inverter nonlinearities and discrete-time vector current control

Abstract: The authors study all-digital discrete-time vector current control loops containing a voltage-fed inverter in series with a permanent magnet synchronous motor. Normal operation of the typical pulse width modulating voltage fed inverter introduces nonlinear distortion into the voltage and the current waveforms of the motor. The authors consider both the causes and the attenuation of these disturbances using all-digital control. An effective, fully digital current controller is developed, and experimental results from a Motorola 68020 microprocessor-based system are presented. >

Analytical transient response of CMOS inverters

Abstract: A general formula relating the waveform at the output of a CMOS inverter to the waveform at its input is derived. The formula is applied to three cases: a step input, a ramp input, and an exponential input. A one-dimensional function dependence of the inverter propagation delay and output slew rate on circuit parameters is derived and an inverter macromodel for timing analysis is suggested and experimentally verified. >

Synthesis techniques for CMOS folded source-coupled logic circuits

Abstract: The application of series-gated, multiplexer-minimization, and variable-entered mapping methods to the synthesis of fully differential CMOS folded source-coupled logic (FSCL) gates is described. In contrast to conventional static logic, FSCL dissipates DC power. Its total power consumption is competitive at higher speeds where its low digital switching noise is most advantageous. The minimum propagation delay of a simple FSCL gate compares favorably to a conventional gate. Complex functions are generally faster in FSCL since its fully differential topology requires fewer stages of delay. Simulated and measured results are presented for several combinational and sequential FSCL gates in a 2- mu m p-well CMOS process. With V/sub dd/=5 V, a FSCL (static) inverter achieved a minimum propagation delay of 400 ps (350 ps) with a power-delay product of 0.5 pJ (0.3 pJ); a FSCL (static) 1-b full adder achieved a minimum delay of 3.0 ns (12.0 ns) with a power-delay product of 0.3 pJ (11.0 pJ). >

Analytical transient response of CMOS inverters

Abstract: A general formula relating the waveform at the output of a CMOS inverter to the waveform at its input is derived. The formula is applied to three cases: a step input, a ramp input, and an exponential input. A one-dimensional function dependence of the inverter propagation delay and output slew rate on circuit parameters is derived and an inverter macromodel for timing analysis is suggested and experimentally verified. >

Programmable driving power of a CMOS gate

Abstract: A CMOS gate is provided which has a programmable driving power characteristic so that its propagation delay time can be varied by digital select control signals (S1-Sm). The CMOS gate includes a programmable inverter section (12) formed of a plurality of inverters (12a-12m), a switching logic control section (14), and a static inverter (16). The switching logic control signal section is responsive to the digital select control signals for selectively programming a certain number of the plurality of inverters to be enabled. In this manner, a certain number of the plurality of inverters will be wired in parallel with the static inverter in order to produce the desired amount of propagation delay time.

A complementary low power non-volatile reconfigurable eecell

Abstract: A non-volatile CMOS electrically erasable programmable memory cell for configuring a PLD is disclosed. A CMOS inverter is formed by fabricating an n-channel MOSFET and a p-channel MOSFET with merged floating gate regions. A tunnel capacitor allows charge to be supplied to or removed from the floating gate. The floating gate provides non-volatile charge storage. The CMOS inverter senses the presence or absence of charge on the floating gate and provides an amplified inverted output. The CMOS inverter consumes very low power and provides rail-to-rail output voltage swings.

Space voltage vector-based new PWM method for large capacity three-level GTO inverter

Abstract: A novel pulse-width-modulation (PWM) method for a three-level inverter based on space voltage vectors is presented. This PWM method can minimize the harmonic components of the output voltage under the minimum pulse-width limitation gate turn-off thyristors (GTOs) and can also suppress the fluctuation of the neural point DC voltage. Experimental results demonstrate that the proposed PWM method is suitable for a large-capacity three-level GTO inverter applied to motor drives for steel rolling mills, railcars, etc. >

Device for driving elevator at service interruption

Abstract: The device for driving an elevator at the time of a service interruption according to the present invention has a circuit for varying d-axis magnetic flux command to prevent regeneative power that can damage the elements in an inverter from being generated at the time of an interruption eliminating the need for a regenerative power consumption circuit.

Cmos digital-controlled delay gate

Abstract: A CMOS digital-controlled delay gate (10) is provided in which the propagation delay time can be precisely controlled by digital select control signals (Sp1-Snm). The delay gate (10) includes an inverter circuit section (12) formed of a plurality of CMOS inverters (12a-12n) each inverter having a P-channel transistor and an N-channel transistor and a control logic section (14,16) which is responsive to the digital select control signals (Sp1-Snm) for changing the ratio of the total P-channel transistor size to the total N-channel transistor size in the enabled transistors. The input threshold voltage of the inverter circuit section (12) is selectively changeable so as to produce a controllable propagation delay.

Interface circuit operable to perform level shifting between a first type of device and a second type of device

Abstract: Interface circuits for connecting gallium arsenide circuits with silicon circuits with the interface circuits using a mix of gallium arsenide and silicon devices. Preferred embodiments (200) connect gallium arsenide buffered FET logic circuits (202) with silicon CMOS circuits with a two branch interface circuit under CMOS supply voltages with a BFL logic branch (208-210) merged with a CMOS inverter branch (204-206).

AC motor drive system with a two phase power supply

Abstract: A motor drive system for driving a conventional single phase PSC motor from a two-phase power source which allows for convenient motor direction reversal. In one embodiment, the PSC motor is supplied from a three-phase inverter that is controlled to generate two-phase power. In another embodiment, the PSC motor is connectable through a double-pole double-throw switch to either a single phase source including a run capacitor or a two-phase inverter source.