Showing papers on "Inverter published in 1994"

Field-weakening performance of brushless synchronous AC motor drives

Abstract: The paper examines the theoretical and practical limitations to the field-weakening performance of surface permanent magnet, synchronous reluctance and interior permanent magnet motors when driven from an inverter with a limited volt-ampere rating. It is shown that the 'optimal' field-weakening performance consists of an infinite constant-power speed range but is limited to an inverter utilisation of about 0.7. The new concept of the interior permanent magnet parameter plane is introduced. This graphically illustrates the effect of varying the drive parameters on the shape of the field-weakening characteristic. The interior permanent magnet parameter plane is used to show that there are three types of optimal field-weakening designs. When practical factors and considerations are taken into account, the optimal high-saliency interior permanent magnet motor design is the most promising for applications requiring a wide field-weakening range. A 7.5 kW design was built and a constant-power speed range exceeding 7.5:1 was demonstrated.

Power losses in PWM-VSI inverter using NPT or PT IGBT devices

Abstract: This paper investigates the power losses for two different IGBT technologies (nonpunch through and punch through) for use in PWM-VSI inverters in order to choose the right device technology for a given application. A loss model of the inverter is developed based on experimental determination of the power losses. The loss model is used on two different modulation strategies which are a sine wave with a third harmonic added and a 60/spl deg/-PWM modulation where only two inverter legs are active at the same time. The two IGBT technologies are characterized on an advanced measurement system which is described. The total power losses in the inverter are estimated by simulation at different conditions and it is concluded that the nonpunch through (NPT) technology is most useful for higher switching frequencies, while the punch through (PT) technology is especially useful at lower switching frequencies and high load currents. It is also concluded that the 60/spl deg/-PWM modulation has the lowest power losses and the power losses are almost independent of phase angle cos(/spl phi/) for normal motor operation. >

Analysis of the impact of pulse-width modulated inverter voltage waveforms on AC induction motors

Abstract: The purpose of this paper is not to reveal any new technology or major breakthrough pertaining to the impact of pulse-width modulated (PWM) adjustable speed drives operating on AC motors. Nor is it to discuss the merits of the various designs of the drives. The applications are also well defined. The area where much confusion still exists deals with the voltage waveform impact on the motor performance, hence, this is the central theme of the paper. The author has assumed that the traditional fundamental sine-wave voltage is (except for starting or outside influences) a steady-state condition, with a maximum and an RMS value, whereas the voltage waveform supplied by a PWM drive can have significant harmonics and transients which may alter the motor performance characteristics and life expectancy. The effects of the maximum voltage, rate of rise, switching frequencies, capacitors, resonance, and harmonics are all considered.

Design considerations for the switched reluctance motor

Abstract: Analytical design equations are developed to predict the performance and to guide the design of the switched reluctance motor (SRM). The use of these analytical equations to trade-off different SRM attributes is discussed. The various approximations and simplifications used in the development of the analytical design equations are justified using results obtained from a detailed computer model of the SRM and by using experimental results from a high power density SRM designed for an aircraft engine fuel pumping application. Comparisons of predicted and measured machine performance parameters for this 90 kW 25000 r/min machine, such as flux linkage curves, back EMF, electromechanical power converted, and inverter voltampere requirements are presented. It is also shown that there exists a fundamental maximum torque density that is attainable with the SRM and an estimate of this maximum torque density limit is given. The power factor for an SRM is defined and the machine parameters that determine its value are presented. This power factor is compared to the similarly defined power factor for an AC machine and found to be smaller. >

Portable pulse oximeter

Abstract: A diagnostic instrument for determining a cardiovascular system parameter. In one embodiment, the instrument takes the form of a portable pulse oximeter comprising a light to frequency converter (LFC) as a sensor. Also provided is a light to frequency converter comprising a photoresistor and capacitor in circuit communication with an inverting Schmitt trigger and configured such that the inverter generates a periodic electrical signal corresponding to the amount of electromagnetic radiation illuminating the photoresistor.

Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay

Abstract: An improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered. These effects modify the ideal linear relationship between the inverter propagation delay and the input ramp rise/fall time by adding a term proportional to the charge supplied by the short-circuiting transistor. This term is shown to contain first- and second-order contributions of the input ramp rise/fall time where the second-order contribution effectively models the propagation delay roll-off for slow input ramps. Both the first and the second-order effects are found to be affected by the P-to-N-channel gain ratio. The model shows excellent agreement with SPICE level 3 simulations; even when the short-circuiting transistor has a driving capability twice that of the charging/discharging transistor the error in the propagation delay is only about 2% for a slow input ramp (input-to-output slope-ratio at V/sub DD//2 equal to 1:2). >

Open loop brightness control for EL lamp

Abstract: An EL lamp characterized by non-linear brightness decay is driven to constant brightness for the life of the lamp by an inverter controlled by a microprocessor. The microprocessor controls the inverter in accordance with a table containing data which is the inverse function of the non-linear brightness decay. The microprocessor tracks the total on-time of the EL lamp and selects the appropriate data from the table for driving the lamp. Control can be analog or digital. If control is analog, the selected data is coupled to a D/A converter which is coupled to the inverter. If control is digital, the selected data is coupled to a counter driving a pulse width modulator which is coupled to the inverter. In accordance with another aspect of the invention, an EL lamp is dimmed a precise amount based upon the data in the table and the EL lamp can be dimmed in unison with other lamp types, each lamp type having a table containing data for dimming.

Inverter models of CMOS gates for supply current and delay evaluation

Abstract: The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also accounted for in the case of series-connected MOSFET's. When combined with our previously reported CMOS inverter model, the peak current is obtained in a time approximately three orders faster than HSPICE with the level-3 MOSFET model. The corresponding accuracy is around 12%. If the current waveform is required, the speed improvement is about an order less. Since the inverter model also yields the delay at no extra cost, the timing of the current waveforms can be done automatically, without recourse to a timing simulator. Although the emphasis here is on CMOS static gates, the method is applicable to dynamic logic gates as well. >

Inverter output voltage synthesis using novel dead time compensation

Abstract: In this paper, a novel dead time compensation method is presented which produces inverter output voltages equal to reference voltages. The experimental result is also presented to demonstrate the validity of the proposed method. It shows that the compensation of the distorted voltage is possible up to sub-microsecond range. The reference voltage can be used as a feedback value, which is essential for sensorless vector control and flux estimation. The method is based on space vector PWM strategy and it can be carried out automatically by an inverter controller for initial set-up without any extra hardware. >

Inverter nonlinearities and discrete-time vector current control

Abstract: This paper studies all-digital discrete-time vector current control loops containing a voltage fed invertor in series with a permanent-magnet synchronous motor. Normal operation of the typical pulse width modulating voltage fed inverter introduces nonlinear distortion into the voltage and the current waveforms of the motor. This paper focuses on both the causes and the attenuation of these disturbances using all-digital control. An effective, fully-digital current controller is developed and experimental results from a Motorola 68020 microprocessor based system are presented. >

Fault mode single-phase operation of a variable frequency induction motor drive and improvement of pulsating torque characteristics

Abstract: Improved reliability and fault tolerant operation of power converter systems are extremely important for industrial AC drives. The paper considers variable frequency variable voltage operation of a three-phase induction motor in single-phase mode for two common faults of a three-phase inverter, i.e., open base drive and device short-circuit. The motor performance has been extensively analyzed in single-phase mode and remedial strategies have been developed to neutralize large second and other lower order harmonic pulsating torques. In a single-phase open loop volts/Hz control made of a faulty three-phase inverter, it has been demonstrated that odd harmonic voltages at appropriate phase angles can be injected to neutralize the low frequency pulsating torques so as to permit smooth drive operation. It has been shown that the pulsating torque can be further reduced by load dependent flux programming rather than operating with constant rated flux. >

Self-diagnostic flame rectification sensing circuit and method therefor

Abstract: An electric control is shown for gas furnaces which controls fan motors and ignition controls based on inputs from a room thermostat (32), a high limit control and an ignition control (14) including a gas valve. A flame sense circuit (42, 42') is coupled to a microprocessor (U2) and includes a flameprobe (P1) energized by line power through a capacitor (C3) via a quick connect (QC31). A capacitor (C4) is charged by a 5 volt DC source through resistor (R12) and inputted to an inverter (U3, S2) which provides a low signal to the microprocessor when no flame is present. When a flame is present the capacitor (C4) discharges through the flame causing the inverter to change state providing a high to the microprocessor indicating that a flame is present. A diagnostic network comprising a low leakage diode (CR10) and serially connected resistor (R11) is coupled between the microprocessor (pin 8) and the input of the inverter (U3) so that the operation of the flame sense circuit can be tested. In an alternate embodiment CMOS switches (S1, S2) are used both to verify that the flame sense circuit is properly wired and to simulate a no-flame condition.

An ideal PWM-VSI inverter using only one current sensor in the DC-link

Abstract: This paper describes how to improve the performance of open loop, low cost PWM-VSI controlled AC machines by the use of one current sensor. The performance is especially improved at low speed where nonlinearities like blanking-time and voltage drop are dominant. An often used modulation technique is described and basic compensation techniques are presented. Only one current sensor in the DC link is used for reconstruction of all three phase currents and the currents are used for compensation. Different limitations are discussed. The compensation techniques are tested in a 16-bit microcontroller based inverter. Tests show that the phase currents can be reconstructed by measurement of the DC link current both at low and high speed. They also show that a highly improved torque-speed characteristic can be obtained by using the compensation techniques and an almost ideal inverter is obtained. >

Current control of a 3-level rectifier/inverter drive system

Abstract: The marriage of a three-level voltage source inverter with a force-commutated three-level rectifier is examined in this paper. Three-level inverters are capable of reducing the output current harmonics dramatically compared with typical two-level inverters whereas a three-level rectifier of this type allows nearly sinusoidal input currents at unity fundamental power factor on the utility side of the drive system. The dual capacitor split voltage bus can be regulated from either the inverter or rectifier side with neutral point balance maintained. This paper address the issues of neutral point voltage control and current regulation from both the rectifier and inverter perspectives. >

Series compensated PWM inverter with battery supply applied to an isolated induction generator

Abstract: This paper proposes a new series compensated induction generator/battery supply topology which provides a constant voltage and frequency at the terminals, allowing minimum current harmonic distortion while at the same time providing a source and sink of real and reactive power. With appropriate control of the reactive power, the speed of the generator is allowed to vary within a relatively wide range. This technique can be further expanded by applying ac capacitors in parallel with the load to lessen the burden of the PWM inverter. Both simulation and experimental results are in agreement with the theory which leads to the conclusion that the system could be feasible for isolated power generation systems (wind, hydro, diesel, or hybrid generation)

Vertically stacked vertical transistors used to form vertical logic gate structures

Abstract: A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with one or more inputs.

Controller for a gas discharge lamp with variable inverter frequency and with lamp power and bus voltage control

Abstract: A high frequency HID ballast includes an inverter for operating the HID lamp at high frequency and an arc instability controller which detects and adjusts the operating frequency of the inverter to avoid acoustic resonance of the discharge arc The ballast ensures that the power delivered to the lamp remains substantially constant despite variations in the gain of the inverter which occur with changes in the operating frequency Power control is accomplished by sensing lamp power and controlling a boost converter to vary the bus voltage feeding the inverter The boost converter is also controlled during lamp ignition, when the load provided by the HID lamp is low, to clamp the bus voltage at a predetermined level The ballast employs universal techniques suitable for operating HID lamps of different types, wattages and manufacturers despite the occurrence of acoustic resonance/arc instabilities among these lamps over a fairly broad frequency range

Level converter including wave-shaping circuit and emulator microcomputer incorporating the level converter

Abstract: A level converter circuit has first and second P-channel transistors having the same first β values, sources of the first and second P-channel transistors being commonly connected to a first potential V1, drains of the first and second P-channel transistors being connected to gates of the second and first P-channel transistors, respectively; first and second N-channel transistors having the same second β values, the first and second N-channel transistors having drains respectively connected to the drains of the first and second P-channel transistors and sources which are grounded; a first inverter for inverting a level-conversion input signal and supplying the inverted signal to the gate of the second N-channel transistor, the first inverter being operated by a power supply of a second potential V2; a second inverter for inverting the output of the first inverter and supplying the further inverted signal to the gate of the first N-channel transistor, the second inverter being operated by a power supply of the second potential V2; and a wave-shaping device for wave-shaping a signal obtained at the junction of the drain of the first P-channel transistor and the drain of the first N-channel transistor. The second β values of the first and second N-channel transistors are more than 50 times as large as the first β values of the first and second P-channel transistors.

An improved voltage vector control method for Neutral-Point-Clamped inverters

Abstract: A new PWM method for Neutral-Point-Clamped (NPC) inverters is introduced. The method is based on closed-loop control of the line-to-line voltage vectors. It uses independent hysteresis comparator controllers to regulate the direct and quadrature axis components of the three phase output voltages. The controllers select the appropriate inverter output voltage vectors through an EPROM table. The closed-loop control allows a high performance over the whole range of operation, even when low speed devices such as the GTO are used. A neutral-point potential control is described, which is capable of stabilizing the variations within fixed limits during steady and transient states. The principle of the method is discussed and the vector selection technique is presented. The effectiveness in the output-voltage-waveform generation and the balance of the DC-link capacitor voltages are verified by simulation and experiment. >

Switched reluctance starter/generator system and method of controlling same

Abstract: A power/generator system controls a turbine engine (14) in a start mode, and converts mechanical energy from the turbine engine (14) to electrical energy in a generate mode. The system comprises a switched reluctance machine (10), an inverter (18) having a dc input/output coupled to the dc distribution bus (20) and coupled to each of the machines (10) phase windings, and a controller (22) to monitor rotor position (30) and generate switching control signals (26) to the inverter (18) for each of the phase windings at a fixed angle prior to alignment of the rotor pole with the associated stator pole, which couples the phase winding to the dc bus (20) and allows dc phase current to energize the winding. At a fixed angle prior to alignment the inverter (18) is controlled to decouple the phase winding from the dc bus (20) and forcing dc current to flow back through diodes to allow the switched reluctance machine to operate as a generator.

A new PWM inverter for photovoltaic power generation system

Abstract: In this paper, the authors propose a novel multi-step PWM inverter for a solar power generation system. The circuit configuration is constructed by adding a bi-directional switch to the conventional bridge type inverter circuit using the isolated DC power supply for which the solar cell is very suitable. The new type of PWM inverter presented has many features such as good output waveform, small size of filter, low switching losses, and low acoustic noise. In this paper the authors describe the circuit configuration, control method and the characteristics of the system, and they also investigate the relation between the inverter and the solar cell characteristics. Finally, some simulation results and experimental results are shown. >

Quasi-linear IGBT inverter topologies

Abstract: Magnetic resonance imaging (MRI) systems require stronger gradient coil currents with faster ramp times for high-speed image taking and in order to obtain a smaller field of view or a magnification effect. Previous speedup inverter circuits able to provide those higher power levels have been discussed at APEC-92 and APEC-93. They could generate squarewave currents with a constant ramp slope determined by the applied high voltage and the coil inductance. Two new circuit topologies are described here which permit the generation of variable ramp as well as sinusoidal current waveforms for the benefit of pulse sequence designers. The result is a novel high-efficiency quasi-linear power amplifier concept. In one case high-frequency pulse-width modulation schemes are replaced by low-frequency baseband switching. Very good sinusoidal current waveforms (150 A peak, 1150 V) have been obtained. >

Inverter circuit for use with discharge tube

Abstract: An inverter circuit for use with a discharge tube or lamp such as a cold-cathode fluorescent lamp, a hot-cathode fluorescent lamp, a mercury arc lamp, a metal halide lamp, a neon lamp or the like is provided. The secondary side circuit of a step-up transformer used in the inverter circuit is constructed as a high frequency power supply circuit and a parasitic or stray capacitance produced in the secondary side circuit of the step-up transformer is utilized as a portion or component of a resonance circuit consisting of an inductive ballast or the inductive output of a leakage flux type step-up transformer and the parasitic capacitance.

Application of GTO voltage source inverter in a hybrid HVDC link

Abstract: This paper investigates the application of a GTO voltage source inverter in a two-terminal HVDC link, which is fed at the sending end by a line-commutated rectifier. This type of HVDC link may be applied when power transfer is predominantly unidirectional, especially to a weak AC system. The investigations are based on analytical studies and digital time-domain simulations with the Electromagnetic Transient program for DC systems (EMTDC). Control method and protection requirements are studied, together with dynamic behavior of the system following disturbances, e.g. DC fault, AC fault, start-up etc. The studies are aimed at exhibiting the technical feasibility of the proposed HVDC scheme. Need for further studies is pointed out when necessary. >

Subthreshold-current reduction circuits for multi-gigabit DRAM's

Abstract: Two subthreshold-current reduction circuit schemes are described to suppress the increase in current in multi-gigabit DRAM's. One is a hierarchical power-line scheme for iterative circuits. In this scheme, a group of circuits is divided into blocks; only the selected block is supplied with power, while the subthreshold current to the many nonselected blocks is reduced. This scheme minimizes the number of circuits carrying the large subthreshold current. Applications of this scheme to word drivers, decoders and sense-amplifier driving circuits are shown. The other scheme is a switched-power-supply inverter with a level holder for random combinational logic circuits. In the active mode of the chip, the operating period of the inverter is distinguished from the inactive period. The inverter is supplied with power only in the operating period, while in the inactive period the subthreshold current is shut off and the output level is kept by the flip-flop level holder. This scheme shortens the period in which the large subthreshold current flows. Both schemes are evaluated for a conceptually-designed 16-Gb DRAM. They reduce its active current by ten-fold from the conventional 1.2 A to 116 mA. >

The LCC inverter as a cold cathode fluorescent lamp driver

Abstract: LCD displays for notebook computers are backlit using cold cathode fluorescent lamps (CCFLs). An investigation of the LCC (series/parallel) resonant inverter as a potential power supply for these lamps is discussed. The attractiveness of this topology is primarily its simplicity compared to the widely used current-fed Royer oscillator based topologies. Experimental comparisons of LCC resonant inverter and Royer inverter performance are presented. >

Synchronously switching inverter and regulator

Abstract: Synchronous switching inverter and regulator suppress rf emissions, and FET push-pull switching for the inverter provides high efficiency power transfer by sinusoidal transformer operation Feedback control for both pass transistors switching and duty cycles insures overall synchronous behavior

Dynamic logic circuit with reduced charge leakage

Abstract: A dynamic logic circuit with reduced charge leakage includes a dynamic complementary MOSFET logic circuit with a P-type MOSFET, a number of N-type MOSFETs and a static CMOSFET inverter circuit. In response to a low clock signal, the P-type MOSFET turns on and charges the precharge node to a precharged node voltage. Some of the N-type MOSFETs are interconnected to form a logic circuit to logically process incoming logic signals and in accordance therewith selectively provide a conduction path for electrical charges from the precharge node. In response to a high clock signal, another N-type MOSFET turns on and together with the logic circuit conditionally discharges the precharge node via the logic circuit conduction path to a discharged node voltage. The value of the discharged node voltage is intermediate to the precharged node voltage and the circuit reference node voltage (e.g. VSS=0). The inverter circuit inverts and buffers the precharged and discharged node voltages. In one embodiment, a bias voltage source, connected between the N-type discharge MOSFET and the reference node, provides a bias voltage which is intermediate to the precharged and reference node voltages, and the discharged node voltage is approximately equal to the bias voltage. In another embodiment, a pull-up MOSFET is connected to the discharge MOSFET for selectively providing a pull-up voltage which is intermediate to the precharged and reference node voltages, and the discharged node voltage is approximately equal to the pull-up voltage.

A sliding mode controller in single phase voltage source inverters

Abstract: This paper deals with a sliding mode controller for a single phase inverter used in UPS applications. The proposed system provides overload and short circuit protection. It can operate in constant or variable frequency. The use of a reduced order observer eliminates the requirement of the load current measurement and improves the noise immunity. Experimental results obtained in laboratory are presented and they confirm the simulation and theoretical analysis. >

Ring oscillator having selectable number of inverter stages

Abstract: A ring oscillator wherein an inverter group includes five inverters (G1 to G5) connected in series, the output of the inverter (G3) is connected to the input of the first inverter (G1) through a transfer gate (TF1), and the output of the inverter (G5) is connected to the input of the inverter (G1) through a transfer gate (TF2). The ring oscillator is adapted such that, when a switching signal (S3) is "L", the CMOS transfer gates (TF1) and (TF2) are on and off, respectively, and the three inverters (G1 to G3) are connected in a loop whereas the inverters (G4, G5) function as buffers receiving the output of the inverter (G3), to provide an oscillation signal (S2) produced by the three inverters (G1 to G3) forming the loop from an output terminal (2) and such that, when the switching signal (S3) is "H", the oscillation signal (S2) produced by the five inverters (G1 to G5) forming the loop is provided, whereby the oscillation signal has a wide range of variable oscillation frequency bands.