Showing papers on "Inverter published in 1996"

Digital integrated circuits: a design perspective

Abstract: (NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.) I. THE FABRICS. 1. Introduction. A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design. 2. The Manufacturing Process. The CMOS Manufacturing Process. Design Rules-The Contract between Designer and Process Engineer. Packaging Integrated Circuits. Perspective-Trends in Process Technology. 3. The Devices. The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling. 4. The Wire. A First Glance. Interconnect Parameters-Capitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future. II. A CIRCUIT PERSPECTIVE. 5. The CMOS Inverter. The Static CMOS Inverter-An Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics. 6. Designing Combinational Logic Gates in CMOS. Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era. 7. Designing Sequential Logic Circuits. Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy. III. A SYSTEM PERSPECTIVE. 8. Implementation Strategies for Digital ICS. From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. Perspective-The Implementation Platform of the Future. 9. Coping with Interconnect. Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip. 10. Timing Issues in Digital Circuits. Timing Classification of Digital Systems. Synchronous Design-An In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives. 11. Designing Arithmetic Building Blocks. Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off. 12. Designing Memory and Array Structures. The Memory Core. Memory Peripheral Circuitry. Memory Reliability and Yield. Power Dissipation in Memories. Case Studies in Memory Design. Perspective: Semiconductor Memory Trends and Evolutions. Problem Solutions. Index.

Inverter output voltage synthesis using novel dead time compensation

Abstract: In this paper, a novel dead time compensation method is presented that produces inverter output voltages equal to reference voltages. An experimental result is also presented to demonstrate the validity of the proposed method. It shows that the compensation of the dead time is possible up to a sub-microsecond range. Also, the reference voltage can be used as a feedback value, which is essential for sensorless vector control and flux estimation. The method is based on space vector pulsewidth modulation (PWM) strategy and it can be carried out automatically by an inverter controller for initial setup without any extra hardware.

Elimination of common mode voltage in three phase sinusoidal power converters

Abstract: This paper presents an active solution to a common-mode voltage created by typical three-phase inverters. It is shown that the addition of a fourth leg to the bridge of a three-phase inverter eliminates the common-mode voltage to ground created by the modulation of the inverter. An appropriate four-phase LC filter is inserted between the inverter and the load in order to create sinusoidal output line-to-line voltage. A simple modification of the modulation strategy is implemented for the four-phase inverter to achieve a three-phase wye-output neutral-to-ground voltage which is equal to zero at all times for an ideal inverter. The modulation strategy thereby completely eliminates the common-mode potential produced by traditional modulation techniques with traditional three-phase inverter topologies.

Unified voltage modulation technique for real time three-phase power conversion

Abstract: In this paper, a novel voltage modulation technique named unified PWM (pulse width modulation) for high performance voltage generation in a voltage-fed inverter is described. As increasing the interest in the high quality power conversion is, a simple PWM scheme that has the wide fitness to the general prospect for the loss minimization and the lowest current harmonic with full DC link voltage utilization is required. From the synthesis of the actual inverter action, a simple but useful concept for the 'effective time' is established. And, fully employing this concept, a new voltage modulation technique for various applications is presented with detailed explanation and actual test results. Implementing this facile strategy to actual fields will result in great reduction of calculation efforts and high applicability including the minimization of switching loss and current harmonics.

Interaction of drive modulation and cable parameters on AC motor transients

Abstract: This paper investigates overvoltage transients on AC induction motors when connected through a cable of arbitrary length to a variable frequency drive (VFD) consisting of a pulsewidth modulation (PWM) inverter with insulated gate bipolar transistor (IGBT) power devices. Factors contributing to a motor overvoltage transient equal to a theoretical twice DC bus voltage are first described using existing transmission line analysis. A critical cable distance I/sub c/ is defined where this 2-pu overvoltage occurs. However, literature is lacking on flow motor voltage transients >2-pu bus voltage and up to 3-4 pu are generated. This phenomenon is observed on all PWM inverters with output cable lengths greater than l/sub c/ distance. Contributing factors to the >2-pu overvoltage phenomenon are investigated by exploring the complex interaction between drive modulation techniques, carrier frequency selected, cable natural frequency of oscillation, cable high-frequency damping losses, and, to a lesser extent, inverter output rise time. Theoretical calculations of cable frequency and damping are correlated with simulation and experimental results. Novel modifications to the PWM modulator, as well as external hardware apparatus, are proposed solutions to the >2-pu overvoltage problem; both are simulated and experimentally confirmed.

Dynamic performance and control of a static VAr generator using cascade multilevel inverters

Abstract: A cascade multilevel inverter is proposed for static VAr compensation/generation applications. The new cascade M-level inverter consists of (M-1)/2 single-phase full bridges in which each bridge has its own separate DC source. This inverter can generate an almost sinusoidal waveform voltage with only one time switching per cycle. It can eliminate the need for transformers in multipulse inverters. A prototype static VAr generator (SVG) system using an 11-level cascade inverter (21-level line-to-line voltage waveform) has been built. The output voltage waveform is equivalent to that of a 60-pulse inverter. This paper focuses on the dynamic performance of the cascade inverter based SVG system. Control schemes are proposed to achieve a fast response which is impossible for a conventional static VAr compensator (SVC). Analytical, simulation and experimental results show the superiority of the proposed SVG system.

Single current sensor technique in the DC-link of three-phase PWM-VS inverters. A review and the ultimate solution

Abstract: This paper proposes an ultimate solution for reconstruction of three phase-currents in a PWM-voltage source inverter by one current sensor in the DC-link, and it gives a review of existing methods in literature and patents. The solution offers fully protection of the inverter including shoot-through of the DC-link, short-circuit of the output phases and earth faults with both low and high impedance. A special configuration in the DC-link can give such features. At the same time a new method to sample the DC-link current is proposed which both can eliminate disturbances from cables between an inverter and an induction motor, and it offers a true simultaneous sample value of all three phase-currents in the center of a switching period. The two methods are implemented in an experimental setup, and test results show that full protection is achieved and the three phase-currents are reconstructed precisely in the whole operating area.

Discrete-time current control of voltage-fed three-phase PWM inverters

Abstract: The discrete-time current control of three-phase voltage-fed pulsewidth modulation (PWM) inverters is discussed, with emphasis on important practical aspects. The inverter feeds a balanced three-phase load of R-L impedances in series with back-EMFs. The inverter-load system is modeled by using space vectors. The practical difficulties of the predictive control method are pointed out. In particular, effects of the delayed application of the manipulated voltage caused by controller computing time are investigated. A modified control law that eliminates the undesirable effects of the computing delay is introduced. Also, prediction of current reference is utilized, which would enable operation with any reference function. An estimation and prediction procedure for the back EMF is also introduced. Steady-state errors in the load current due to these predictions are calculated for sinusoidal operation. Simulation results for the predictive control and the modified control laws are presented and discussed.

Pulse-density-modulated power control of a 4 kW, 450 kHz voltage-source inverter for induction melting applications

Abstract: This paper presents a 4 kW, 450 kHz voltage-source inverter with a series resonant circuit for induction melting applications, which is characterized by the power control based on pulse density modulation (PDM). The pulse-density-modulated inverter makes an induction melting system simple and compact, thus leading to higher efficiency. A modulation strategy is proposed to realize the induction melting system capable of operation at the frequency and power level of interest. Some interesting experimental results are shown to verify the validity of the concept.

Discrete sliding-mode control of a PWM inverter for sinusoidal output waveform synthesis with optimal sliding curve

Abstract: This paper presents a discrete sliding-mode control scheme with feedforward compensation for the closed-loop regulation of the pulse-width modulated (PWM) inverter used in an uninterruptible power supply (UPS). The proposed feedforward controller can effectively improve the tracking performance of the PWM inverter. In designing the sliding-mode controller, we have taken load disturbance into consideration to enhance the robustness of the PWM inverter. Moreover, the upper bound of the load disturbance under which the sliding condition can be maintained has also been derived. The sliding curve of the sliding-mode controller is designed such that the behavior of the controlled PWM inverter is optimal subject to the selected cost function. Due to the coordinate transformation proposed in this paper, only the output voltage needs to be measured as feedback for the purpose of closed-loop regulation. Simulation and experimental results are given to show the effectiveness of the proposed control scheme.

Deadbeat control of a three-phase inverter with an output LC filter

Abstract: The discrete-time control of a three-phase inverter with an output LC filter is described based on space vectors. The mathematical model of the inverter-filter system is first obtained by using space vectors to represent three-phase quantities. Deadbeat control laws are derived for no-load and resistive-load cases. Then, a deadbeat control law is obtained for the case when the load draws current of any waveshape from the inverter-filter. It is shown that deadbeat control of output voltage can be achieved in two control steps. The manipulated variable, which is the voltage vector demanded from the inverter, is implemented using the space vector modulation technique. Simulation results for various operating conditions are presented.

Circuit for dimming compact fluorescent lamps

Abstract: A dimming control circuit provides power from an ac source to a compact fluorescent lamp. The circuit generally includes a resonant half-bridge inverter driven by a pulse-duration-modulated voltage, for providing a high-frequency ac voltage between the lamp electrodes. A combination inductive and capacitive snubber circuit reduces switching losses in the inverter and increases the efficiency of the dimming circuit. A low-voltage transformer connected across the resonant portion of the inverter provides voltage to heat the lamp filaments. The filament voltage is substantially constant over a range of pulse-durations providing a dimming range from about 100% to 1% of full light output. A power supply circuit having a power factor of about 0.95 provides both high-voltage and low-voltage dc power to the dimming circuit with minimal losses. A shutdown circuit is provided to shut off power to the lamp if the dimming circuit is miswired or a ground fault occurs.

A new panel-integratable inverter concept for grid-connected photovoltaic systems

Abstract: This paper describes the problems of conventional inverter concepts for photovoltaic power systems and presents a new, panel-integratable inverter concept as a solution. This concept is advantageous regarding safety (no DC-lines), flexibility (modular concept), converted energy per year (no mismatch losses due to individual MPP tracking of each panel) and costs (no reinforced isolation due to AC distribution). Furthermore a 250 W DC to AC inverter is developed, which consists of a series resonant DC-DC power converter and a line inverter. The inverter has a high efficiency and consumes little power itself. Meeting international standards, sinusoidal line current with low distortion is achieved. The inverter has a built-in controller to operate the panel in the maximum power point. Above this, the concept allows the flexible use with many different combinations of solar panels. To realize an inexpensive system, the controller is built up using standard low-cost components.

Measurement and reduction of EMI radiated by a PWM inverter-fed AC motor drive system

Abstract: This paper presents theoretical and experimental relationships between radiated electromagnetic noises and common-mode and normal-mode currents, paying attention to an induction motor drive system fed by a voltage-source pulsewidth modulation (PWM) inverter. A method of reducing both currents is proposed, based on an equivalent model, taking into account parasitic stray capacitors inside an induction motor. Electromagnetic interference (EMI) radiated by a 3.7-kW induction motor drive system is actually measured, complying with the VDE 0871 Class A [3 m]. Experimental results verify that the combination of the already proposed common-mode transformer (CMT) and the normal-mode filters (NMFs) being proposed in this paper is a practically viable and effective way to reduce EMI resulting from both common-mode and normal-mode currents.

A study of equipment sizes and constraints for a unified power flow controller

Abstract: This paper provides a quantitative measurement of the benefit that a unified power flow controller (UPFC) can provide to increase firm power transfer between two large power systems Included is a complete model for a UPFC control system that contains bus voltage control by the shunt inverter, real power transfer between the shunt and series inverters, and real and reactive power control for the transmission line into which the series inverter is inserted A significant part of the model is representation of dynamic limits that coordinate injected current limits for the shunt inverter, power transfer limits between inverters, voltage injection limits for the series inverter, current limits for the series inverter and line voltage limits for the transmission line This paper contains a simple power system simulation to demonstrate the coordinated dynamic control and illustrate issues that power system planning engineers consider in defining applications for a UPFC

A 50-150 kHz half-bridge inverter for induction heating applications

Abstract: A half-bridge resonant-type IGBT inverter suitable for heating magnetic and nonmagnetic materials at high-frequency is described A series-parallel arrangement of capacitors is adopted and an optimum mode of operation is proposed In this mode, the inverter is operated at unity power factor by PLL control irrespective of load variations, with maximum current gain, maximum overall system efficiency, and practically no voltage spikes in the devices at turn-off The actual performance was tested on a 50-150 kHz prototype rated at 6 kW The low-cost developed hybrid inverter is characterized by its simplicity of design and operation, yet is versatile in performance A simplified analysis and detailed experimental results are presented

Class DE inverters and rectifiers for DC-DC conversion

Abstract: A new family of Class DE inverters and related rectifiers is presented. Based on the Class D RF inverter, the circuits feature Class E switching transitions (zero voltage, zero dv/dt), giving low switching losses despite device capacitance and stored charge, combined with low voltage stress. Matching between inverter and rectifier is considered, time reversal duality is introduced and a family of inverters and rectifiers is presented. The circuits should find application in megahertz DC-DC converters.

Novel grid-connected photovoltaic inverter

Abstract: Detailed analysis and simulation results of a novel solar photovoltaic inverter configuration interconnected to the grid are presented. From the simulation results it is confirmed that the harmonic distortion of the output current waveform of the inverter fed to the grid is within the stipulated limits laid down by the utility companies. Typical hardware aspects are also discussed in detail and the applicability of the design is verified.

Design considerations for an inverter output filter to mitigate the effects of long motor leads in ASD applications

Abstract: In this paper, design considerations for an inverter output filter to mitigate the effects of long motor leads in ASD applications are presented. It is shown by analysis that for a given length of cable, reducing the dv/dt of the PWM inverter output voltage applied to the cable below a critical value will eliminate overvoltages due to voltage reflections. Design issues for a low pass filter at the inverter output terminals to reduce the dv/dt of the inverter output pulse are examined in detail. The filter operation is verified for the entire variable frequency range of the inverter. The performance of the filter is evaluated in simulation, and experimentally on a 208 V L-L system and on a 480 V commercially available AC motor drive (PWM IGBT). The proposed inverter output filter is then compared with a motor terminal shunt filter also designed to reduce overvoltages and ringing at the motor terminals.

PV water pumping with a peak power tracker using a simple six step square wave inverter

Abstract: The application of photovoltaics (PV) has been increasingly popular, especially in remote areas where power from a utility is not available or is too costly to install. PV powered water pumping is frequently used for agriculture and in households. Among many available schemes, the system under study consists of a PV array, a variable-frequency inverter, an induction motor, and a water pump. The inverter feeds the induction motor, which drives the water pump. To seek the optimum power output of the PV array, the inverter is operated at variable frequency to vary the output of the water pump. The inverter is operated to generate a six-step quasi-square wave instead of a pulse width modulated (PWM) voltage output to reduce the switching losses. The inverter acts as both a variable-frequency source and a peak-power tracker of the system, thus having the number of switches minimized. The system is a low-cost design with a simple control strategy. The direct current (DC) bus is supported by a DC capacitor; thus, a balance-of-power flow must be maintained to avoid the collapse of the DC bus voltage. Another advantage of the system is that the current is limited to an upper limit of the PV array current. Thus, in case a short circuit is developed, the motor winding and the power semiconductor switches can be protected against excessive current flow.

A capacitive threshold-logic gate

Abstract: A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

A low-voltage, low-power CMOS delay element

Abstract: A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 /spl mu/m CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current. The inherent advantage of a CMOS thyristor in low voltage domains enables this delay element to work down to the supply voltage of 1 V while the threshold voltage of the nMOS and pMOS transistors are 840 mV and -770 mV, respectively. The designed delay value is less sensitive to supply voltage and temperature variation than RC-based or CMOS inverter-based delay elements. Temperature compensation and jitter performance in a noisy environment are also discussed.

Inverter control method and inverter apparatus using the method

Abstract: A pulse width of a pulse train signal used for PWM (pulse width modulation) control is monitored. When a variation of the pulse width substantially disappears within a specified time, it is determined that an operating point on an output characteristic curve of a photovoltaic array is located on the open-circuit voltage side of a maximum power point. When the variation of the pulse width does not disappear after the elapse of the specified time, it is determined that the operating point is located on the short-circuit current side of the maximum power point. Based on the determination result, the inverter control is performed such that the operating point follows the maximum power point.

Control of square-wave inverters in high power hybrid active filter systems

Abstract: This paper presents a new control scheme for a hybrid parallel active filter (HPAF) system intended for high-power applications-up to 100 MW nonlinear loads-to meet IEEE 519 recommended harmonic standards. The active filter inverter is realized with small-rated (1%-2% of the load rating) square-wave inverters operating at the dominant harmonic frequencies. The proposed system achieves harmonic isolation at desired dominant harmonic frequencies, such as the fifth and seventh, even in the presence of supply voltage harmonic distortions. A novel method of active filter inverter DC-bus control, as proposed here, achieves power balancing by exchanging energy at the fundamental frequency and at the dominant harmonic frequency (such as the fifth). The proposed square-wave inverter-based HPAF system provides improved filtering characteristics as compared to the conventional passive filter and is expected to be cost effective for high-power nonlinear loads compared to the conventional passive filter or other active filtering solutions. The concept of harmonic isolation at dominant harmonic frequencies by square-wave inverters with the proposed control scheme is validated by simulation results.

Analysis and controller design of static VAr compensator using three-level GTO inverter

Abstract: A static VAr compensator (SVC) using a three-level GTO voltage source inverter (VSI) is presented for high-voltage, high-power applications. The three-level VSI has lower harmonic components and higher DC-link voltage than the two-level VSI and thus can be operated at lower switching frequency (f/sub sw/<500 Hz) without excessive harmonic contents. From the DQ-transformed equivalent circuit of the presented SVC system, DC and AC analyses are carried out to find the steady-state and the dynamic characteristics of the system. Based on the open-loop transfer function of the system, a controller is designed to achieve fast dynamic response. The experimental results confirm the theoretical analyses and controller design.

A new SOI inverter for low power applications

Abstract: The speed degradation in CMOS circuits with the supply voltage reduction is an important obstacle in the scale down of supply voltage. Thus, many attempts to reduce the gate delay have been tried using the dynamic threshold scheme. However, they have limitations in the operation voltage and large leakage current. We propose a new type of SOI inverter gate which has considerably shortened circuit delay with similar energy consumption in the conventional SOI CMOS circuit at low voltage operation. It uses the positive-body bias effect that enhances drain currents when the body is biased positively. The operation principle of the proposed gate, the optimal circuit and device conditions studied by simulations, and the fabrication and measurement data are reported in this paper.

Converter-fed subsea motor drives

Abstract: A subsea adjustable-speed motor fed via a long cable in the range of several tens of kilometers between the converter and the motor are analyzed by simulations. Due to resonance, one critical frequency range occurs where significant generation of harmonics from the inverter should be avoided. A voltage source inverter is more feasible than a current source inverter since it is easier to modify the output waveform in order to avoid resonance problems. The resistive voltage drop in the long cable reduces the air-gap torque of the motor, particularly at low frequencies. This causes a problem for the start-up of the motor due to stiction torque. A start-up strategy is envisaged which is a compromise between voltage boost, inverter current, and transformer core dimensions. In normal operation mode the inverter voltage is proportional to the frequency. An open speed loop is used which keeps the system stable for potential load variations. The results from a 1-MW full-scale system test are summarised.

A novel soft-switched PWM inverter for AC motor drives

Abstract: A novel soft-switched inverter topology is derived from the passively clamped quasi-resonant link (PCQRL) circuit. By introducing magnetic coupling between the two resonant inductors, the number of auxiliary switches can be reduced from two to one, and only a single magnetic core is required for the resonant DC link. An analysis of this novel PCQRL topology with coupled inductors is presented to reveal the various soft-switching characteristics. In comparison with the conventional passively clamped, continuously resonant DC link inverter, this soft-switched inverter can reduce voltage stresses from more than 2 per unit (pu) to 1.1-1.3 pu. It can also provide soft-switched pulse-width modulated (PWM) operation. Simulations and experiments are performed to backup the analysis.

Active power conditioner for reactive and harmonic compensation having PWM and stepped-wave inverters

Abstract: An active power quality conditioner for compensating reactive power and harmonic distortion in power systems. A pulse width modulated (PWM) inverter (70) for each phase is controlled to produce a harmonic distortion compensation signal that is coupled to an inductor. The inductor is connected in series between a stepped-wave inverter (84) and one phase of the power line. A current produced by the stepped-wave inverter compensates for the reactance of a load coupled to the power line. The PWM inverter operates at a frequency that is substantially greater than the fundamental frequency of the power line and is not exposed to the full power line voltage; it can be constructed using components of relatively low power and voltage rating. In contrast, the stepped-wave inverter, which is decoupled from the PWM inverter, operates at the fundamental frequency and is subjected to most of the stress. Both shunt coupled and series coupled compensators are described. Compensation for an unbalanced load is provided using a compensator (364) that includes a 24-pulse stepped-wave inverter (366).

Back-gate forward bias method for low-voltage CMOS digital circuits

Abstract: The back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process have been set up against latch-up, parasitic bipolar, impact ionization, and stand by current. Following these guidelines, a cost-effective low power, low-voltage, high-density mixed mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.