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Showing papers on "Junction temperature published in 2000"


Patent
22 Sep 2000
TL;DR: In this article, a calibrated isothermal assembly for a thermocouple thermometer is provided to obviate a calibration step after manufacture of the instrument, which includes a memory device containing stored calibration data specific to the temperature sensor.
Abstract: A calibrated isothermal assembly for a thermocouple thermometer is provided to obviate a calibration step after manufacture of the instrument. A compact isothermal block is fabricated on a specialized printed circuit board which includes a thick metal plate to establish sufficient thermal mass and good heat conductivity. A temperature sensor is mounted at the thermocouple reference junction on the printed circuit board to track the reference junction temperature. The calibrated isothermal assembly also includes a current source for the temperature sensor, and a memory device containing stored calibration data specific to the temperature sensor.

183 citations


Patent
John W. Oglesbee1
23 Oct 2000
TL;DR: A series current regulator with an on-silicon temperature sensor (102) formed over current battery protection device (100) regulates current in a pass element (101) linearly while sensing the junction temperature of the pass element(101) as discussed by the authors.
Abstract: A series current regulator with an on-silicon temperature sensor (102) formed over current battery protection device (100) The protection device (100) regulates current in a pass element (101) linearly while sensing the junction temperature of the pass element (101) If the temperature of the pass element (101) reaches a predetermined threshold, the on-silicon temperature sensor (102) actuates a switch (104) which causes the pass element (101) to go into a high impedance mode The protection device offers advantages over positive temperature coefficient (PTC) and further includes faster trip time and lower leakage current

168 citations


Patent
31 Oct 2000
TL;DR: In this article, a thermocouple is used to generate voltage indicative of a junction temperature, and a memory device is connected to the thermocourer and the memory device to store data.
Abstract: A device and method for measuring temperature is disclosed. The device, for example, can include a thermocouple configured to generate a voltage indicative of a junction temperature; a memory device configured to store a unique device ID and to store data; a logic unit connected to the thermocouple and the memory device; an I/O interface connected to the logic unit, the I/O interface configured to communicate with a computer system; and an internal temperature sensor connected to the logic unit, the internal temperature sensor configured to determine a cold junction temperature.

130 citations


Journal ArticleDOI
TL;DR: In this paper, the mean device junction temperature of heterojunction bipolar transistors (HBTs) under high self-heating operating conditions is extracted using three trivial DC measurements of the device where the junction temperature is known to be the same.
Abstract: A new technique is presented that can directly extract the mean device junction temperature of heterojunction bipolar transistors (HBTs) under high self-heating operating conditions. The method uses three trivial DC measurements of the device where the junction temperature is known to be the same. This paper details the technique and applies it to both closely and widely spaced multi-finger HBT's, and compares the results to methods already known.

83 citations


Journal ArticleDOI
Tien-Yu Lee1
TL;DR: In this paper, the authors presented a novel approach to optimize pin array design of an integrated, liquid-cooled, insulated gate bipolar transistor (IGBT) power module with the aid of a computational fluid dynamics (CFD) code.
Abstract: This paper presents a novel approach to optimize pin array design of an integrated, liquid-cooled, insulated gate bipolar transistor (IGBT) power module. With the aid of a computational fluid dynamics (CFD) code, the fluid field and heat transfer inside the module were analyzed, and several design options on pin arrays were examined. For IGBT die circuitry, the uniformity of temperature distribution among dies is as critical as the magnitude of the die temperature. A noticeable variation in temperature among dies can accelerate the thermal runaway and reduce the reliability of the devices. With geometrically-optimized-pin designs located both upstream and downstream of the channel, a total power dissipation of 1200 W was achieved. The maximum junction temperature was maintained at 100/spl deg/C and the maximum variation among dies was controlled within 1/spl deg/C. The results from this study indicated that the device junction temperatures were not only reduced in magnitude but were equalized as well. In addition, the maximum power dissipation of the module was enhanced. Comparison with other direct- (pool boiling) and indirect- (cold plate) liquid cooling techniques was also discussed.

65 citations


Journal ArticleDOI
TL;DR: Rodgers et al. as discussed by the authors evaluated the predictive accuracy of a commercial CFD code for both natural and forced convection heat transfer of single and multicomponent printed circuit boards (PCBs).
Abstract: The application of computational fluid dynamics (CFD) analysis for the thermal design of electronic systems has the potential to enable accurate solutions to be generated and quickly assessed. With the use of validated numerical models, numerical analysis can also be used to provide useful insights into heat transfer processes which could otherwise be difficult to characterize experimentally. However, the capabilities of the CFD tool need to be carefully evaluated so as to provide a degree of confidence in prediction accuracy, thereby minimizing the need to qualify thermal designs. Such an evaluation is presented in this paper, which represents the culmination of a benchmark study by Rodgers et al. [1999]. This overall study assesses the predictive accuracy of a commercial CFD code for both natural and forced convection heat transfer of single- and multicomponent printed circuit boards (PCBs). Benchmark criteria were based on both component junction temperature and component-PCB surface temperature profiles. In the context of the overall study, this paper brings these analyses together to provide a more comprehensive assessment of CFD predictive accuracy for component junction temperature. Additionally the validated numerical models are used to further investigate the sensitivity of component heat transfer to convective environment, both natural and forced, component position relative to the PCBs leading edge, impact of upstream aerodynamic disturbance, and the representation of PCB FR4 thermal conductivity. The significance of the listed variables is quantified by analyzing predicted component energy balances. Qualitative descriptions of the fluid flow fields obtained using a novel paint film evaporation technique are also provided in this study. Both analyses yield new insights of the heat transfer processes involved and sources of numerical error.

51 citations


Patent
30 Aug 2000
TL;DR: In this paper, an integrated heat sink that can provide heat dissipation from multiple components mounted on a circuit board with each component having a different height dimension relative to each other is described.
Abstract: An integrated heat sink that can provide heat dissipation from multiple components mounted on a circuit board with each component having a different height dimension relative to each other is described. The heat sink has a first face on which a plurality of cooling fins are formed and a second face on which at least one pedestal is formed. The pedestal has a contacting surface to thermally couple to at least one of the multiple components to dissipate heat therefrom. The heat sink is designed to prevent a junction temperature at the contact area where the heat sink and each of the components abut one another from exceeding a maximum design value for the system. In one embodiment of the present invention, the heat sink has a groove formed in the second face. A conductive gasket is disposed in the groove and contacts a metal trace on the circuit board when the heat sink is attached to the circuit board to form a Faraday cage or EMI shield.

50 citations


Journal ArticleDOI
TL;DR: In this paper, a vector error-corrected active load-pull system is presented for the characterization of microwave power transistors under coherent pulsed RF and pulsed DC operating conditions.
Abstract: This paper presents a new automated and vector error-corrected active load-pull system allowing the characterization of microwave power transistors under coherent pulsed RF and pulsed DC operating conditions. In this paper, the use of this system is focused on the characterization of a 240-/spl mu/m/sup 2/ GaInP-GaAs heterojunction bipolar transistor (HBT) (Thomson CSP-LCR, Orsay, France). On one hand, source and load-pull measurements of such a transistor are reported for different pulsewidths. On the other hand, nonlinear simulations based on an electrothermal model of an HBT have been performed and are compared with experiments. Power variations and RF carrier phase shift within the pulse versus input power and junction temperature of the transistor are shown.

43 citations


Patent
11 Jan 2000
TL;DR: In this article, a thermal joint for facilitating heat transfer between two components is described, which is formed from an alloy of at least two constituents, i.e., a liquid temperature and a solid temperature.
Abstract: A thermal joint for facilitating heat transfer between two components is described. The thermal joint is formed from an alloy of at least two constituents. The alloy has a liquid temperature and a solid temperature. When the operating temperature falls between the liquid temperature and the solid temperature, the alloy has at least one liquid phase which is in substantial equilibrium with at least one solid phase. The thermal joint is used between a heat-generating component, such as a semiconducting device, and a heat-dissipating component, such as a heat sink. Such thermal joint substantially reduces the thermal resistance between the two components.

35 citations


Journal ArticleDOI
TL;DR: In this article, the steady state thermal performance of an isolated SO-8 package is experimentally characterized on five thermal test printed circuit boards (PCBs) and the results compared against corresponding numerical predictions.
Abstract: The steady state thermal performance of an isolated SO-8 package is experimentally characterized on five thermal test printed circuit boards (PCBs) and the results compared against corresponding numerical predictions. The study includes the low and high conductivity JEDEC standard, FR4 test PCBs and typical application boards. With each PCB displaying a different internal structure and effective thermal conductivity, this study highlights the sensitivity of component operating temperature to the PCB, provides benchmark data for validating PCB numerical modeling methodologies, and helps one assess the applicability of standard junction-to-ambient thermal resistance (/spl theta//sub JA/) data for design purposes on nonstandard PCBs. Measurements of junction temperature and component-PCB surface temperature distributions were used to identify the most appropriate modeling methodology for both the component and the PCB. Based on these results, a new PCB modeling methodology is proposed that conserves the need for modeling detail without compromising prediction accuracy.

34 citations


Journal ArticleDOI
TL;DR: Thermal stability of high-frequency insulated gate bipolar transistor (IGBT) operation is studied and the nonpunch-through IGBT is found to be stable when operated within its rated temperature.
Abstract: Thermal stability of high-frequency insulated gate bipolar transistor (IGBT) operation is studied in this paper. The nonpunch-through IGBT is found to be stable when operated within its rated temperature. Thermal runaway occurs with punch-through IGBTs at temperatures below the maximum junction temperature when operated at high frequency at well below rated current, with snubber or soft-switching circuits.

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate the use of finite element techniques for modelling thermal fatigue effects in solder layers of insulated gate bipolar transistor (IGBT) modules used in traction applications.

Journal ArticleDOI
TL;DR: In this paper, a central composite design of experiments can be applied to provide a more accurate thermal characterization of a multichip module package, which can be used by the customer to calculate individual device junction temperatures over a wide variation of convection cooling environments and multiple device power dissipations.
Abstract: The steady state thermal performance of semiconductor packages has been traditionally reported through the utilization of a single junction-to-ambient thermal resistance constant commonly referred to as /spl theta//sub ja/. This is particularly inadequate for multichip modules where several devices reside within the same package structure. This paper discusses how a central composite design of experiments can be applied to provide a more accurate thermal characterization of a multichip module package. The end product is a series of linear or polynomial equations which can be utilized by the customer to calculate individual device junction temperatures over a wide variation of convection cooling environments and multiple device power dissipations. A 352 plastic ball grid array package, which encompasses three individual integrated circuit devices, is used as an example. The paper steps through the sensitivity analysis and evaluates the accuracy of the resulting equations. This method of thermal characterization can be easily applied to single chip modules of varying power and cooling regimes, or multiple output devices where several power junctions reside within the same integrated circuit.

Proceedings ArticleDOI
23 May 2000
TL;DR: In this article, the impact of printed circuit board (PCB) design on component operating temperature was quantified by measuring the steady state thermal performance of four package types (PSO20: heat slug up, PSO20, heat slug down, LFBGA80 and SBGA352) on up to six different, single-component thermal test PCBs in the standard natural and forced convection environments.
Abstract: As the functionality of electronic systems increase, so does the complexity of printed circuit board (PCB) design, with greater component packing densities requiring additional internal signal, power and ground layers to facilitate interconnection. The extra copper content introduced increases PCB thermal conductivity and heat spreading capability, which can strongly influence component operating temperature. Therefore, this experimental study sought to quantify the impact of PCB construction on component operating temperature and relate this sensitivity to the package design, PCB effective conductivity and convective environment. This was achieved by measuring the steady state thermal performance of four package types (PSO20: heat slug up, PSO20: heat slug down, LFBGA80 and SBGA352) on up to six different, single-component thermal test PCBs in the standard natural and forced convection environments. Test velocities ranged from 0.5 m/s to 5.0 m/s and all test components contained a thermal test die. Measurements of junction temperature and component-PCB surface temperature distributions are both presented for power dissipation levels within the range 0.5 to 6.0 Watts. The study includes the low and high conductivity JEDEC standard, FR4-based test PCBs and typical application boards. As each PCB had a different internal structure and effective thermal conductivity, this study highlights the sensitivity of component operating temperature to the PCB, provides benchmark data for validating numerical models, and helps one assess the applicability of standard junction-to-air thermal resistance (/spl theta//sub JA/ and /spl theta//sub JMA/), as well as both junction-to-board (/spl Psi//sub JB/) and junction-to-top (/spl Psi//sub JT/) thermal characterisation parameters for design purposes on nonstandard PCBs.

Proceedings ArticleDOI
Y.S. Chung1, B. Baird
10 Dec 2000
TL;DR: In this article, the problem of the electrical-thermal coupling (ETC) phenomena based on a LDMOS device through theoretical and experimental analyses is treated, and an ETC driven snapback breakdown, "Hot-snapback", is discussed to explain the decrease in the safe operating area (SOA), both voltage and current.
Abstract: The continuing march for reduction of feature size and enhancement of the functional integration is now seriously challenged by the limited capability in handling increased power dissipation, not only in power electronics but also in the field of VLSI and ULSI. Interaction between the electrical and thermal energy generated by self-heating is fundamental in understanding this power dissipation limit and safe operating area (SOA) of the semiconductor devices in both transient and steady-state operations. This work treats the problem of the electrical-thermal coupling (ETC) phenomena based on a LDMOS device through theoretical and experimental analyses. This report discusses an ETC driven snapback breakdown, "Hot-snapback", to explain the decrease in SOA, both voltage and current. The "Hot-snapback" process is much more favorable for explaining the device failure mechanism typically observed at the center of the thermal mass than the "intrinsic junction temperature" theory.

Patent
17 Oct 2000
TL;DR: In this article, a PWM power converting device, the state of a load is monitored and the difference in the junction temperatures in the case of a light load and in a heavy load becomes small, so that the power cycle and thermal fatigue life time are improved.
Abstract: PROBLEM TO BE SOLVED: To improve life time of a main circuit element, without deteriorating its controllability. SOLUTION: In a PWM power converting device, the state of a load is monitored. When the load is light, a carrier frequency for PWM is increased, the switching frequency of a main circuit element is increased, the switching loss is increased, and a junction temperature of the element is increased. When the load is heavy, however, the carrier frequency is decreased, the switching frequency of the main circuit element is decreased, the switching loss is decreased and the junction temperature of the element is decreased. The difference in the junction temperatures in the case of a light load and in the case of a heavy load becomes small, so that the power cycle and thermal fatigue life time are improved. The carrier frequency may be changed only when the load is light.

Patent
26 Sep 2000
TL;DR: In this paper, a ripple temperature detector is used to measure the ripple temperature from the base plate temperature detection value in the unit measuring period of operation/stop by a temperature range, a counter counts the number of the times of generation for each ripple temperature every unit measurement period, and a life time calculation part 16 estimates the life time L(1/CD) from an accumulated damage rate.
Abstract: PROBLEM TO BE SOLVED: To solve such a problem that it takes labor and time to estimate the life time of a semiconductor power converter and life time prediction based on the number of the time of switching of an element, but life time prediction becomes rough when based on the junction temperature. SOLUTION: A temperature detector 10 measures the base plate temperature of IGBT of an inverter 2, a ripple temperature detector 13 measures the ripple temperature from the base plate temperature detection value in the unit measuring period of operation/stop by a temperature range, a counter 14 counts the number of the times of generation for each ripple temperature every unit measuring period, a power damage rate calculation part 15 finds an accumulated damage rate CD from the number of the times of the life time by temperature range for the ripple temperature and the number of the times of practical generation, and a life time calculation part 16 estimates the life time L(=1/CD) from an accumulated damage rate.

Proceedings ArticleDOI
23 May 2000
TL;DR: In this article, a new approach was proposed to analyze the progressive performance degradation of the power electronics owing to the growth of thermomechanically induced fatigue cracks within the package bonds and interconnects.
Abstract: The coupled effects of mechanical stress and thermal performance on the electrical function of power electronics are combined within a new analytical framework designated thermomechatronics The result is a new approach to analyzing the progressive performance degradation of the power electronics owing to the growth of thermomechanically induced fatigue cracks within the package bonds and interconnects The present analysis focuses on relating the consequences of such cracks on the thermal resistance of the package, which governs the junction temperature of the electronics for fixed power dissipation The rate of track growth during operation is then analyzed based on closed-form analytical solutions combined with physically based failure modes for the relevant materials Finally, the manner in which the present results may be integrated with conventional circuit simulation tools is described

Proceedings ArticleDOI
15 Aug 2000
TL;DR: In this paper, the junction temperature of power devices was found out based on the power losses of IGBT devices and the transient thermal impedance model, and the comparison between experiment using a 50 A/600 V IGBT module and calculation results shows that this method is effective.
Abstract: The junction temperature of IGBT is the key factors that could influence the whole system's reliability and efficiency. An electro-thermal method was implemented to estimate the junction temperature of IGBT devices in this paper. The junction temperature of power devices was found out based on the power losses of IGBT devices and the transient thermal impedance model. The comparison between experiment using a 50 A/600 V IGBT module and calculation results shows that this method is effective.

Patent
30 Aug 2000
TL;DR: In this article, a motor driving control device that achieves as high as possible phase coil energization level while preventing thermal destruction of the power switching element by using precise thermal detection of a portion of the Power switching element inside a switching module of the control device is used for calculating a saturation temperature Tjgoal.
Abstract: A motor driving control device that achieves as high as possible phase coil energization level while preventing thermal destruction of the power switching element by using precise thermal detection of a portion of the power switching element inside a switching module of the control device. An electric power loss Lt at the switching element is used for calculating a saturation temperature Tjgoal. On the basis of the saturation temperature, Tjgoal, and a time constant τ of temperature rise, an instant junction temperature Tjnow is calculated. A difference Error between the instant junction temperature Tjnow and an upper temperature limit value Tjmax is calculated. In a motor locked condition, a coefficient Kt is calculated for the target torque, the target torque being equal to the required torque multiplied by Kt. Kt is based on the Error for calculating the target torque. If Error is greater than or equal to a predetermined value, K3, Kt is set to be 1, even if Kt is in excess of 1. If Error is less than or equal to 0 , Kt is set to be zero.

Journal ArticleDOI
TL;DR: In this paper, the effect of reverse diode recovery on the turn-on losses of a fast Si IGBT was studied both at room temperature and at 150°C, and the results showed that the reverse recovery can reduce the turn on losses by as much as 10× at 25°C and between 5× and 18× at 150 °C.
Abstract: Recent progress in Silicon Carbide (SiC) material has made it feasible to build power devices with reasonable current density. This paper will present recent results including a comparison with state of the art silicon diodes. The effect of diode reverse recovery on the turn-on losses of a fast Si IGBT are studied both at room temperature and at 150°C. At room temperature, SiC diodes allow a reduction of IGBT turn on losses by as much as 6× and at 150°C junction temperature SiC diodes allow a turn-on loss reduction of between 16× and 3× when compared to fast and ultra fast silicon diodes respectively. Total losses due to reverse diode recovery were reduced by as much as 10× at 25°C and between 5× and 18× at 150°C. The yield and I – V characteristics of these diodes are also described.

Journal Article
TL;DR: In this paper, a three dimensional analysis of the heat and fluid flow over a single 84 pins PLCC package mounted on a Printed Circuit Board (PCB) along the direction of flow is carried out as a conjugate heat transfer problem using the CFD code, FLUENTTM under mixed convection regime.
Abstract: Miniaturization has led to higher dissipation rates with more stringent restraints on thermal management. Conduction analysis alone (with heat transfer coefficient based on correlations, which are not directly applicable to actual cases) is not adequate to determine the junction temperature and the thermal resistance. A conjugate analysis with the board removes the uncertainty in the specification of the convective heat transfer coefficient. Therefore, a three dimensional analysis of the heat and fluid flow over a single 84 pins PLCC package mounted on a Printed Circuit Board (PCB) along the direction of flow is carried out as a conjugate heat transfer problem using the CFD code, FLUENTTM under mixed convection regime. In this simulation, the effects of air flow, leaded versus leadless PLCC, presence and absence of the mother board, and its thermal conductivity on junction temperature and thermal resistance have been investigated. It has been observed from the analysis that the increase in air flow velocity reduces the junction temperature and the thermal resistance. The presence of leads acts as mini heat sinks thus reducing the junction temperature. Mother board acts as a conducting wall and thereby the maximum temperature of the junction is reduced considerably. Increase in the thermal conductivity of the board further reduces the junction temperature. Subsequently, the results obtained are used to understand the package’s thermal performance.

Patent
21 Mar 2000
TL;DR: In this paper, a polysilicon (10) is integrated into an MOS-gated power semiconductor, and an integrated circuit is employed to sense the junction temperature of the power-sensor device.
Abstract: A polysilicon (10) is integrated into an MOS-gated power semiconductor, and an integrated circuit is employed to sense the junction temperature of the power semiconductor device. To compensate for process variations in the manufacture of the polysilicon resistor, the integrated circuit (20) is self-trimming to adapt to the resistor (10). The circuit determines the optimum current to match the respective room temperature resistance of the polysilicon resistor, and stores a related value. The temperature of the power semiconductor device is measured by generating a constant current through the resistor that has a magnitude proportional to the stored value. Overtemperature protection may also be provided. To adapt the resistance (10), at initial use of the semiconductor, counter 22 is enabled and controls current mirror 23 to send a step-rise increasing current through sense resistor (10). When the voltage across the resistor reaches a predetermined value (0.87 V bg ), comparator 35 disables the counter and its state is read into EEPROM 31. This self-trimming causes a measurement current which ensures that at the critical temperature e.g. 170‹C, the voltage across sense resistor (10) causes comparator 36 to output a signal.

Journal ArticleDOI
TL;DR: In this article, the authors characterized the dependence of self-clamped inductive switching (SCIS) energy capability on the clamp voltage for an ambient temperature range of -50 to 175/spl deg/C.
Abstract: Self-clamped inductive switching (SCIS) energy capability is the most important device parameter for insulated gate bipolar transistors (IGBTs) used in automotive ignition applications. We have experimentally characterized the dependence of IGBTs SCIS energy capability on the clamp voltage for an ambient temperature range of -50 to 175/spl deg/C. It is found that the SCIS energy of an IGBT increases by nearly 70% when the clamp voltage is reduced from 400 to 100 V. Such a significant increase is attributed to the lower maximum junction temperature that is reached in an IGBT with a lower clamp voltage during the SCIS testing. Two-dimensional (2-D) electrothermal device simulations have been performed to analyze such phenomena. The results provide critical information for device design and product development.

Patent
05 Dec 2000
TL;DR: In this article, a boundary temperature defined at the boundary between a first temperature range and a second temperature range is defined, where the boundary temperature is 180°C or more (e.g., 370°C) higher than the Curie temperature.
Abstract: The semiconducting ceramic material of the present invention containing BaTiO 3 and having a positive temperature coefficient of resistance is endowed with high withstand voltage. In the semiconducting ceramic material, a boundary temperature defined at the boundary between a first temperature range and a second temperature range is 180° C. or more (e.g., 370° C.) higher than the Curie temperature, wherein the first temperature range is higher than the Curie temperature and the ceramic material has a positive temperature coefficient of resistance in the range, and the second temperature range is higher than the first temperature range and the ceramic material has a negative temperature coefficient of resistance in the range.

Proceedings ArticleDOI
23 May 2000
TL;DR: In this paper, the authors describe a suitable constant temperature fixture to keep a test vehicle at a constant temperature for power levels of up to 65 W, where a power diode in bare die form is used as the heating source.
Abstract: This paper describes a technique for measuring cooling curves at power levels of up to 65 W. The paper describes in detail a suitable constant temperature fixture to keep a test vehicle at a constant temperature for these power levels. In this experiment a power diode in bare die form is used as the heating source. The diode V/sub f/ is used for junction temperature sensing. The cooling curve method of temperature characterisation is used at this power level because heating curves are difficult to measure when special designed thermal test chips are not available. A special test vehicle was designed to obtain equal temperature distribution across the test diode. The test vehicle has a three layer structure to minimise the number of thermal layers. This enables a more precise cooling curve analysis later in this project. The experimental results were correlated through the use of CFD models. From these CFD models, the thermal resistance and thermal capacitance of the die attach layer can be evaluated. This experiment is part of a project, the objective of which is to thermally characterise die-attach materials for power applications.

Proceedings ArticleDOI
18 Jun 2000
TL;DR: In this paper, the analysis of cooling curves for power levels of up to 65 W is presented, where the tooling curve method of temperature characterisation is used instead of the widely used heating curve measurement because at this power level heating curves are difficult to obtain when specially designed thermal test chips are not available.
Abstract: In this paper the analysis of cooling curves for power levels of up to 65 W is presented. The paper details a constant temperature fixture to keep a test vehicle at a constant temperature for these power levels. The test vehicle consists of a special designed copper block, a die attachment layer and a bare die for heating and sensing. The diode V/sub f/ is used for sensing junction temperature. The tooling curve method of temperature characterisation is used instead of the widely used heating curve measurement because at this power level heating curves are difficult to obtain when specially designed thermal test chips are not available. The design of the special test vehicle is presented in detail. It is designed to achieve an equal temperature distribution across the test diode. The test vehicle has a three-layer structure to minimise the number of thermal interfaces. This enables a more precise cooling curve analysis later in this work. The experimental results were correlated through the use of CFD models and thermal equivalent electrical networks. From these CFD models, the thermal resistance and thermal capacitance of the die attach layer can be evaluated. A network model is used to implement the thermal performance in network analyser tools such as SPICE. The paper shows a good agreement between the CFD model, the lumped thermal network and the measurements.

Patent
06 Nov 2000
TL;DR: In this article, the number of a plurality of second diodes (1 CD) constituting the second diode part (1 C) was shown to be equal to the number (1 BD) of first diode parts.
Abstract: A first diode part ( 1 B) for sensing junction temperature and a second diode part ( 1 C) for absorbing static electricity that are included in a semiconductor element ( 1 ) for electric power are formed within the same substrate together with a semiconductor element part ( 1 A) for electric power. Moreover, the number of a plurality of second diodes ( 1 CD) constituting the second diode part ( 1 C) is equal to the number of a plurality of first diodes ( 1 BD) constituting the first diode part ( 1 B). In addition, a capacitor ( 11 ) for reducing the impedance is disposed between the input terminals of a forward direction voltage fall operating amplifying circuit part ( 4 ) of a controlling circuit part ( 8 ). Here, it is effective to form an LC low pass filter as well by covering a forward path side relay lead part ( 9 A) and a backward path side relay lead part ( 9 B) with one tubular ferrite core.

Patent
31 Mar 2000
TL;DR: In this paper, a voltage Vbe between a base and an emitter to be applied to a transistor is monitored at the respective levels, where Vbe is an abscissa axis and Ta is an ordinate axis, ΔTa/ΔPower is calculated, and a thermal resistance is obtained.
Abstract: PROBLEM TO BE SOLVED: To accurately obtain a junction temperature in a real testing state. SOLUTION: A level of the ambient temperature Ta is deflected at two points or more, and a level of a predetermined power Power to be applied is deflected at least two points or more. A voltage Vbe between a base and an emitter to be applied to a transistor is monitored at the respective levels. A Ta-Vbe graph is drawn, wherein Vbe is an abscissa axis and Ta is an ordinate axis, ΔTa/ΔPower is calculated, and a thermal resistance is obtained. Further, a junction temperature Tj at the time of testing is obtained by a formula of (Tj (tch)) = Ta + thermal resistance × Power) from the temperature Ta at the time of the real testing and the predetermined power Power.

Proceedings ArticleDOI
Jae-Kwan Kim1, Chul-Hi Han
23 Jan 2000
TL;DR: In this article, a thermal infrared detector using temperature characteristics of a diode is proposed and developed, which utilizes electrochemical etching technique to achieve the thermal isolation of the diode.
Abstract: A new thermal infrared detector using temperature characteristics of a diode is proposed and developed. Micromachined isolated silicon diode for IR detection (MISIR) utilizes electrochemical etching technique to achieve the thermal isolation of the diode. Very high dependence on the junction temperature of the diode enables high responsivity of the MISIR and electrochemical etching provides effective isolation with simple and low-cost process. The fabricated MISIR exhibits the detectivity of 1.2/spl times/10/sup 10/ (cm Hz/sup 1/2 //W) under air ambient at room temperature.