Showing papers on "Junction temperature published in 2019"
TL;DR: In this article, a 3D coupled electrothermal model was constructed based on the electrical and thermal characterization results of a MOSFET fabricated via homoepitaxy.
Abstract: The ultrawide bandgap (UWBG) (~4.8 eV) and melt-grown substrate availability of $\beta $ -Ga2O3 give promise to the development of next-generation power electronic devices with dramatically improved size, weight, power, and efficiency over current state-of-the-art WBG devices based on 4H-SiC and GaN. Also, with recent advancements made in gigahertz frequency radio frequency (RF) applications, the potential for monolithic or heterogenous integration of RF and power switches has attracted researchers’ attention. However, it is expected that Ga2O3 devices will suffer from self-heating due to the poor thermal conductivity of the material. Thermoreflectance thermal imaging and infrared thermography were used to understand the thermal characteristics of a MOSFET fabricated via homoepitaxy. A 3-D coupled electrothermal model was constructed based on the electrical and thermal characterization results. The device model shows that a homoepitaxial device suffers from an unacceptable junction temperature rise of ~1500 °C under a targeted power density of 10 W/mm, indicating the importance of employing device-level thermal managements to individual Ga2O3 transistors. The effectiveness of various active and passive cooling solutions was tested to achieve a goal of reducing the device operating temperature below 200 °C at a power density of 10 W/mm. Results show that flip-chip heterointegration is a viable option to enhance both the steady-state and transient thermal characteristics of Ga2O3 devices without sacrificing the intrinsic advantage of high-quality native substrates. Also, it is not an active thermal management solution that entails peripherals requiring additional size and cost implications.
82 citations
TL;DR: In this paper, a temperature-dependent short-circuit performance of a Gen3 10-kV/20-A silicon carbide (SiC) mosfet was analyzed.
Abstract: This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet . The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μ s is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. A thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.
67 citations
TL;DR: In this article, the authors proposed a thermal balance control scheme to keep the junction temperature of both devices within a specified temperature range, and to minimize the total power loss simultaneously, and investigated the dependency of the hybrid switch switching losses on the gate control pattern both theoretically and experimentally.
Abstract: The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC mosfet offers an improved cost/performance tradeoff in power converters. Currently, the gate control strategy of these two internal devices emphasizes on minimizing the total power loss, and is referred to as the efficiency control mode in this paper. However, there is a serious risk of overheating and reliability degradation of the SiC mosfet if solely relying on this control strategy. In this paper, we propose a new method of gate control optimization, referred to as the thermal balance control mode, to keep the junction temperature of both devices within the specified temperature range, and to minimize the total power loss simultaneously. We first investigate the dependency of the hybrid switch switching losses on the gate control pattern both theoretically and experimentally. We then extensively study control optimization in these two distinct control modes in a dc–dc boost converter. It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode, but much lower and more balanced junction temperatures of the two internal devices. Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability in the 20-kHz boost converter or four times higher switching frequency in the 4-kW boost converter than a single IGBT solution with hard switching condition, and yet a considerably lower component cost than a single SiC mosfet solution in the boost converter.
61 citations
TL;DR: In this paper, an intelligent gate drive for online junction temperature monitoring of silicon carbide (SiC) devices based on turn-off delay time as the thermo-sensitive electrical parameter is proposed.
Abstract: Junction temperature is an important design/operation parameter, as well as, a significant indicator of device's health condition for power electronics converters. Compared to its silicon (Si) counterparts, it is more critical for silicon carbide (SiC) devices due to the reliability concern introduced by the immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn- off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn- off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 and approach 736 ps/°C tested in the case study with little penalty on the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn- off delay time in real time with the resolution less than 104 ps. As a result, the micro-controller is capable of “reading” junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with an intelligent gate drive consisting of the gate impedance regulation circuit and online turn- off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.
58 citations
TL;DR: In this article, the authors investigated the heat dissipation performance of AlN ceramic substrate in high-power LEDs and found that the thermal conductivity of the AlN substrate is a promising candidate for high power LEDs.
53 citations
TL;DR: The critical components, namely SiC power devices and modules, gate drives, and passive components, are introduced and comparatively analyzed regarding composition material, physical structure, and packaging technology, as well as MEMS devices.
Abstract: The significant advance of power electronics in today's market is calling for high-performance power conversion systems and MEMS devices that can operate reliably in harsh environments, such as high working temperature. Silicon-carbide (SiC) power electronic devices are featured by the high junction temperature, low power losses, and excellent thermal stability, and thus are attractive to converters and MEMS devices applied in a high-temperature environment. This paper conducts an overview of high-temperature power electronics, with a focus on high-temperature converters and MEMS devices. The critical components, namely SiC power devices and modules, gate drives, and passive components, are introduced and comparatively analyzed regarding composition material, physical structure, and packaging technology. Then, the research and development directions of SiC-based high-temperature converters in the fields of motor drives, rectifier units, DC-DC converters are discussed, as well as MEMS devices. Finally, the existing technical challenges facing high-temperature power electronics are identified, including gate drives, current measurement, parameters matching between each component, and packaging technology.
53 citations
TL;DR: In this article, the authors present the process of designing liquid-cooled micro-channel heat sink fin geometries based on a numerical method, topology optimization, which is developed to find designs that satisfy heat transfer requirement with low pressure drop penalty.
52 citations
TL;DR: The observer technology makes this paper the first to realize closed-loop control of averaged temperatures achieving an increased robustness and insensitivity to modeling errors, and a key element of the active thermal cycle reduction algorithm is the virtual heat sink that derives feasible and stress-relieving thermal trajectories.
Abstract: This paper proposes a methodology for active thermal control of power electronic modules in ac applications, which includes a loss manipulation unit, a thermal observer structure, and an active thermal cycle reduction algorithm. It aims to reduce the thermo-mechanical strain in the inter-connects of the module in order to enhance its reliability and lifetime. The loss manipulation unit operates in a minimally invasive manner by manipulating adaptive gate resistances and the pulsewidth modulation frequency. This allows the individual thermal control of multiple devices within a power module, which has not been achieved in prior work. A thermal observer structure that estimates averaged junction temperatures by combination of a thermal model and sensor information is introduced. The observer technology makes this paper the first to realize closed-loop control of averaged temperatures achieving an increased robustness and insensitivity to modeling errors. A key element of the active thermal cycle reduction algorithm is the virtual heat sink that derives feasible and stress-relieving thermal trajectories. The trajectories are applied with a unique thermal feedback control that smoothly manipulates the averaged junction temperature of the power module even in the presence of loss manipulation limits. The active thermal control methodology is evaluated experimentally with a state-of-the-art insulated-gate bipolar transistor (IGBT) power module.
48 citations
TL;DR: In this article, the impact of operation current on the degradation behavior of 310nm UV LEDs was investigated over 1000h of stress, and it was shown that lifetime is inversely proportional to the cube of the current density.
Abstract: The impact of operation current on the degradation behavior of 310 nm UV LEDs is investigated over 1000 h of stress. It ranges from 50 to 300 mA and corresponds to current densities from 34 to 201 A/cm2. To separate the impact of current from that of temperature, the junction temperature is kept constant by adjusting the heat sink temperature. Higher current was found to strongly accelerate the optical power reduction during operation. A mathematical model for lifetime prediction is introduced. It indicates that lifetime is inversely proportional to the cube of the current density, suggesting the involvement of Auger recombination.
47 citations
46 citations
TL;DR: A compact thermal real-time model enables the computation of device losses and temperatures at critical locations within a power module, e.g., at the devices, solder interfaces or the base plate, on a conventional digital signal processor.
Abstract: This paper presents a methodology for real-time monitoring of 3-D temperature distributions and device losses within power electronic modules. It allows precise thermal management, empirical lifetime prognosis, and detection of critical degradation of the power module. By effective combination of thermal 3-D finite difference modeling, parametric loss models, and model truncation techniques, a compact thermal real-time model is derived. It enables the computation of device losses and temperatures at critical locations within a power module, e.g., at the devices, solder interfaces or the base plate, on a conventional digital signal processor. The real-time model as well as real-time junction temperature information are combined in a new Luenberger-style observer structure. Applying bandwidth partitioning, the observer estimates the temperatures throughout the power module every switching period and averaged over one excitation period with nearly zero lag, even if the junction temperature measurement exhibits delays and has noisy signals. Furthermore, it estimates errors in the loss prediction process that can be tracked over the lifetime of the power module to detect degradation of the devices or the power module. The observer and its features are experimentally evaluated under realistic operating conditions on a load emulator using a state-of-the-art automotive power module.
TL;DR: In this paper, the authors used the phonon Monte Carlo (MC) method to investigate the thermal spreading resistance in a ballistic-diffusive regime for gallium-nitride (GaN) high-electron-mobility transistors.
Abstract: To develop an efficient thermal design for gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) that usually hold a super-high-power density, it is essential to accurately predict the junction temperature. In GaN HEMTs, the heat transfer process is dominated by thermal spreading resistance. Moreover, the phonon mean free paths (MFPs) of GaN are comparable with the channel layer thickness and the heat spot width. Thus, a ballistic effect emerges, resulting in the invalidity of Fourier’s heat conduction law. Therefore, Fourier’s law-based thermal resistance model should be reexamined and modified for this case. In this paper, we used the phonon Monte Carlo (MC) method to investigate the thermal spreading resistance in a ballistic-diffusive regime for GaN HEMTs. Our simulation results indicate that the ballistic effect significantly altered the temperature distributions within channel layers and resulted in a dramatic increase in the thermal resistance when compared with Fourier’s law-based predictions. Furthermore, a semiempirical thermal resistance model with a fitting parameter was derived. This model can accurately address the issues of thermal spreading and the ballistic effect. This paper can provide a more in-depth understanding of the thermal spreading resistance in a ballistic-diffusive regime, and it can be useful for the prediction of junction temperatures and for the thermal management of HEMTs.
TL;DR: In this paper, the authors proposed to monitor the thermal parameters of insulated gate bipolar transistor (IGBT) module using the case temperature, which is able to eliminate the influence of thermal interface material (TIM) degradation on the monitored results.
Abstract: In this paper, we propose to monitor the thermal parameters of insulated gate bipolar transistor (IGBT) module using the case temperature. This method works during the shutoff period of IGBT module where the case temperature is in the cooling phase By establishing the relationship between the Cauer-type thermal RC parameters and the time constants of case temperature cooling curves, thermal parameters of the IGBT module can be identified. The proposed method is able to eliminate the influence of thermal interface material (TIM) degradation on the monitored results, which is quite challenging for the current case temperature monitoring methods. Moreover, it enables the detection of thermal resistance and thermal capacitance of the TIM and that of the IGBT module at the same time. Experimental tests are performed to validate the accuracy and feasibility of the proposed method. Moreover, impacts of the junction temperature, case temperature sensing position, and thermal coupling on the monitored results are analyzed.
TL;DR: In this article, an adaptive thermal equivalent circuit model that can estimate the junction temperature of IGBTs with precision under solder aging conditions was proposed, where two thermal sensors were placed at the interface between the baseplate and the cold plate.
Abstract: Implementation of real-time health assessment and thermal management of insulated gate bipolar transistors (IGBTs) require thermal equivalent circuit models that can be used to predict the junction temperature of the modules. Solder aging in IGBTs has a substantial impact on the accuracy of junction temperatures estimated by the models. This paper proposes an adaptive thermal equivalent circuit model that can estimate the junction temperature of IGBTs with precision under solder aging conditions. First, the solder aging process is monitored in real time by the temperature gradient of the baseplate of the IGBT module, which is easily implemented by placing two thermal sensors at the interface between the baseplate and the cold plate. Then, when the solder aging is detected, the actual junction temperature obtained by an ON-state collector–emitter voltage of the IGBT is utilized to update model parameters based on the thermal behavior of the device. By combining the two stages, the effect of solder aging on the accuracy of the junction temperature estimate is removed in time. Simulation and experimental results are provided to verify the effectiveness of the proposed method.
TL;DR: In this paper, the effects of unbalanced internal pressure, which occurs frequently within large-scale press-pack modules, remain unclear, and thermal parameters within modules cannot be directly measured due to the pressure-type package structure.
Abstract: Press-pack packaging technology has been widely used in insulated-gate bipolar transistors for high-voltage and high-power density applications. The effects of unbalanced internal pressure, which occurs frequently within large-scale press-pack modules, remain unclear, and thermal parameters within modules cannot be directly measured due to the pressure-type package structure. Current and temperature distribution within 3300 V/1500 A modules are investigated to determine module reliability characteristics and derive future lifetime models using multiphysics models. Unbalanced clamping force causes extremely uneven temperature stress and electrical stress in spatial distribution. It indicates that partial chips must withstand high stresses that cause the initial fatigue of large-scale press-pack modules. Junction temperature difference reaches up to 53.6 °C among chips at chip surface roughness of $1.27~\mu \text{m}$ . This condition shows that the aging of modules will accelerate at the onset of partial chips degradation. Finite-element modeling and equivalent test are utilized to verify the multiphysics model by using single-chip devices in parallel.
10 Dec 2019
TL;DR: In this paper, the performance of a liquid cooling system on the junction temperature of a high-power inverter drive utilizing three legs of half-bridge modules (CAS120M12BM2 Silicon Carbide CREE MOSFETs) was investigated.
Abstract: The most important key in the thermal management of power electronic devices is the cooling system design. One of the most promising cooling techniques is indirect liquid cooling using cold plates. This paper studies the performance of a liquid cooling system on the junction temperature of a high-power inverter drive utilizing three legs of half-bridge modules (CAS120M12BM2 Silicon Carbide CREE MOSFET). One of the primary objectives is to compare the effect of different geometries and boundary conditions on the thermal performances regarded as maximum junction temperature. Based on the analysis of the liquid cooling, different boundary conditions are proposed and a comparison of the main case study is made against the case of different geometries and boundary conditions. Furthermore, the concept of varying the distance between three half-bridge MOSFETs in an inverter drive is introduced. According to the simulation results, in the best combination, the maximum junction temperature of the module is decreased to 82.2°C when the thermal paste and NX100 materials are selected for the thermal interface material and the heat sink, respectively. In addition, Simulation results show that the best distance between each of the modules in the inverter drive is 10mm spacing.
TL;DR: In this article, a double-sided 1200-V/600-A multichip half-bridge insulated gate bipolar transistor (IGBT) module was fabricated utilizing molybdenum as stress-relief buffer and sintered nanosilver as die-attachment.
Abstract: A double-sided 1200-V/600-A multichip half-bridge insulated gate bipolar transistor (IGBT) module was fabricated utilizing molybdenum as stress-relief buffer and sintered nanosilver as die-attachment. By using the double-sided packaging, the volume, parasitic inductance, and junction temperature were decreased significantly, and thus the higher power density could be achieved. However, the thermomechanical stress was also increased. In this paper, molybdenum instead of the most common copper was used as a stress-relief buffer between chips and substrate, and thus the thermomechanical stress decreased greatly without significantly increasing the junction temperature. Specifically, by using molybdenum instead of copper as the buffer material, the simulation results showed that the IGBT junction temperature at total power loss of 200 W only increased by 5.2% (2.22 °C), but the corresponding thermomechanical stress decreased by 9.8% (5.58 MPa), and the sintering residual stress decreased by 20.1% (48.88 MPa). Thermal performance, static and dynamic electrical performance, and reliability via power cycling test of the double-sided module were also characterized experimentally. No degradation of the power devices proved that the way to double-sided packaging power devices could be used for future manufacturing of high-power density power module.
TL;DR: In this paper, the authors performed numerical and experimental study of minichannel heat sinks (MCHS) with air as a cooling medium, using full domain simulation in ANSYS Fluent.
TL;DR: In this article, the avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT.
Abstract: In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT. The experimental results show that SiC MOSFET can handle ∼20% higher avalanche energy at the same current density, and ∼50% higher current density at the same amount of energy. As SiC device has 5× smaller chip size, the advantage will disappear when comparison is performed with avalanche current. To improve the avalanche current capability of SiC MOSFET, failure mechanisms are analyzed. At first, the junction temperature is calculated with V-T model and thermal model, from which a linear dependence of temperature on avalanche current is revealed. Then, the probability of parasitic BJT turn-on is modeled analytically with the base-to-emitter resistance/voltage, which is found to be highly dependent on the p+ ohmic contact resistance (ρc) and base doping concentration (NB) designs of the device. Based on the modeling results, at the peak junction temperature 650 K in UIS test, the BJT turn-on can already be triggered for SiC MOSFET. The failure trigger temperature can be raised with a higher NB and lower ρc design, thus the avalanche current capability can be increased accordingly. On the other hand, with a much deeper p+ body structure design, the Si IGBT can prevent the BJT latch-up failure. Based on the failure analysis, a trench source structure of SiC MOSFET is proposed to further improve the avalanche capability for smaller chip size design.
TL;DR: In this paper, an online junction temperature extraction method is proposed based on the electroluminescence phenomenon of the body diode of SiC power mosfet s, which ascribes to the radiative recombination in the low doped region of the chip.
Abstract: Accurate information of the junction temperature of SiC power mosfet s ensures safe operation and helps reliability assessment of the devices. In this paper, an online junction temperature extraction method is proposed based on the electroluminescence phenomenon of the body diode of SiC power mosfet s. It is found that during the forward conduction interval of the body diode, visible blue light is emitted around the chip, which ascribes to the radiative recombination in the low doped region of SiC mosfet s. Experimental results suggest the light intensity changes linearly with the variation of the temperature and behaves as a temperature sensitive optic parameter (TSOP). Further, an electro-thermal-optic model is proposed to reveal the relationship between the electroluminescence intensity, forward current, and junction temperature. Based on the TSOP, an online junction temperature extraction method is proposed for SiC mosfet s and verified in an SiC mosfet based inverter. Compared with state-of-the-art methods, the proposed junction temperature measurement method is contactless and immune from the aging of the package.
TL;DR: In this paper, a power stage design approach for a high power density air-cooled inverter, which involves the utilization of emerging 1.7kV silicon carbide (SiC) mosfet bare die engineering samples, heatsinks optimized with genetic algorithm, and built using three-dimensional printing technology and integrated power modules with a novel packaging structure, is presented.
Abstract: This article presents a systematic power stage design approach for a high-power density air-cooled inverter, which involves the utilization of emerging 1.7 kV silicon carbide (SiC) mosfet bare die engineering samples, heatsinks optimized with genetic algorithm, and built using three-dimensional printing technology and integrated power modules with a novel packaging structure. The developed air-cooled inverter assembly is mainly composed of the SiC mosfet phase leg modules with split high-side and low-side switch submodules, which are attached to two separate heatsinks for increased heat dissipation area and reduced thermal resistance. The heatsink is designed using a co-simulation environment with finite element analysis in COMSOL and genetic algorithm in MATLAB. The primary design procedure, including bare die device characterization, loss calculation, thermal evaluation, and power module development, is elaborated. The proposed design approach is verified and validated through experiments at each stage of development. The experimental results show that the inverter California Energy Commission efficiency is 98.4%, and a power density of 75 W/in3 is achieved with a sufficient junction temperature margin for semiconductor long-term reliability.
TL;DR: This letter experimentally demonstrates the temperature dependence of the flatband voltage in high-power insulated-gate bipolar transistors and investigates the practical use of this temperature dependence as an addition to the genre of IGBT junction temperature measurement methods known as temperature sensitive electrical parameters (TSEPs).
Abstract: This letter experimentally demonstrates the temperature dependence of the flatband voltage ( V FB) in high-power insulated-gate bipolar transistors (IGBTs). The gate voltage during the turn- on delay is shown to fluctuate up to 5 mV/°C as a result of this temperature dependence. We investigate the practical use of this temperature dependence as an addition to the genre of IGBT junction temperature measurement methods known as temperature sensitive electrical parameters (TSEPs). This letter will outline some possible measurement circuits and highlight issues with V FB that may make its use as a TSEP problematic.
TL;DR: An automated design and optimization methodology for air-cooled heatsinks are proposed based on genetic algorithm and finite element analysis and results show that the optimized heatsink is superior over a customized solution by 27% less in size and 6% lower in junction temperature.
Abstract: Heatsink design is critical for power density and reliability enhancement of power semiconductor modules. In this letter, an automated design and optimization methodology for air-cooled heatsinks are proposed based on genetic algorithm and finite element analysis. While the genetic algorithm generates a population of candidates with complex heatsink cross-section geometry in each iteration, finite element analysis is used to evaluate the fitness function of individual heatsink, i.e., junction temperature of semiconductor devices. With the rule of “survival of the fittest,” the proposed methodology eventually converges to an optimum heatsink design with the lowest device junction temperature. The optimized heatsink is fabricated through three-dimensional printing technology for thermal performance evaluation. Simulation and experimental evaluations have been conducted based on a 50-kW three-phase air-cooled inverter with the fabricated heatsinks. The comparative evaluation results show that the optimized heatsink is superior over a customized solution by 27% less in size and 6% lower in junction temperature.
TL;DR: In this article, a root cause analysis of thermal power saturation in broad area diode lasers is presented, where an extreme triple asymmetric vertical design is introduced, that enables devices to be realized that show minimized degradation of internal differential efficiency with temperature and therefore increased performance in CW operation.
Abstract: A root-cause analysis of thermal power saturation in broad area diode lasers is presented. Thermal power saturation limits in largest parts the optical power in continuous wave (CW) driven diode lasers, as junction temperature increases with bias. Accordingly, gain decreases and, hence, the carrier density in the quantum well increases (nonpinning) to compensate the low gain and the additional photon loss. A systematic variation of epitaxial designs was used to experimentally clarify the impact of modal gain on the temperature dependence of differential internal efficiency and optical loss. To account for this effect in simulation, a rate equation model was applied to determine temperature dependent slope efficiency. Longitudinal spatial hole burning (LSHB) causes an asymmetry of the carrier density profile, leading to high nonlinear carrier loss at the back facet, but also the average carrier density increases with temperature, enhancing the impact of LSHB. This enhancement effect leads to rapid degradation of internal differential efficiency with temperature and, hence, early power saturation. The extreme triple asymmetric vertical design is introduced, that enables devices to be realized that show minimized degradation of internal differential efficiency with temperature and therefore increased performance in CW operation.
TL;DR: In this article, a millimeter-scale liquid metal droplet thermal switch capable of controlling heat transfer spatially and temporally is presented, which can balance the device heat transfer rate and enhance junction temperature uniformity and system reliability.
Abstract: Heat dissipation is a key obstacle to achieving reliable, high-power-density electronic systems. Thermal devices capable of actively managing heat transfer are desired to enable heat dissipation optimization and enhanced reliability through device isothermalization. Here, we develop a millimeter-scale liquid metal droplet thermal switch capable of controlling heat transfer spatially and temporally. We demonstrate the thermal switch by integrating it with gallium nitride (GaN) devices mounted on a printed circuit board (PCB) and measure heat transfer and temperature of each device for a variety of switch positions and heat dissipation levels. When integrated with a single GaN device (2.6 mm $\times4.6$ mm face area) dissipating 1.8 W, the thermal switch shows the ability to actively control heat transfer by conducting 1.3 W in the ON mode with the GaN device at 51 °C ± 1 °C, and 0.5 W in the OFF mode with the GaN device at 95 °C ± 1 °C. To elucidate the heat transfer physics, we developed a 1-D system thermal resistance model in conjunction with an independent 3-D finite-element method (FEM) simulation, showing excellent agreement with our experimental data. Finally, we demonstrated that when the switch is integrated with two GaN devices, the switch can balance the device heat transfer rate and enhance junction temperature uniformity and system reliability by lowering the device-to-device temperature difference from > 10 °C (no switch) to 0 °C.
TL;DR: In this article, a model of high power light-emitting diode package integrated with micro-thermoelectric cooler and explore the performance of this system under various interfacial and size effects.
TL;DR: In this paper, a thermal network parameter estimation method for insulated-gate bipolar transistor (IGBT) modules using the junction temperature cooling curve is proposed, which finds the RC parameters of a fourth-order Cauer network by establishing a relationship between RC parameters and time constants of junction temperature response curves.
Abstract: This paper proposes a thermal network parameter estimation method for insulated-gate bipolar transistor (IGBT) modules using the junction temperature cooling curve. The proposed method finds the RC parameters of a fourth-order Cauer network by establishing a relationship between RC parameters and time constants of junction temperature response curves. Experimental tests are performed to validate the accuracy of the developed method. Results show that the difference of total thermal resistance between the proposed method and IEC standard is below 2%. Advantages of the proposed method over the existing methods are that the proposed method does not need 1) to know the power loss information of IGBT and 2) to heat the IGBT module up to thermal steady state. In addition, we show that the identified RC parameters can be used for condition monitoring and junction temperature estimation.
TL;DR: The neutral-point-shift-based active thermal control method, which can reshape the MMC ac voltage and balance the three-phase dc current, is proposed, and the thermal distribution among three phases becomes balanced and the junction temperature of the most stressed power device is significantly reduced.
Abstract: The thermal design of a highly reliable modular multilevel converter (MMC) is significant for the voltage-source-converter-based high-voltage direct current system, especially under the unbalanced ac grid fault. In this paper, the analytical thermal model of the MMC considering the fault ride-through strategy is established to explore the MMC dynamic thermal behavior under the single-phase-to-ground fault. With the established thermal model, the proportional relationship between the MMC dc current and submodule thermal imbalance factor is derived. By exploring the features of dc current, it is discovered that the asymmetrical ac voltage makes the dc current different among three phases, leading to the thermal imbalance among three phases. To solve this issue, the neutral-point-shift-based active thermal control method, which can reshape the MMC ac voltage and balance the three-phase dc current, is proposed. With the proposed control method, the thermal distribution among three phases becomes balanced and the junction temperature of the most stressed power device is significantly reduced. Furthermore, the performance analysis shows that the proposed method brings little effects on the circulating current suppression. Finally, the major theoretical conclusions are verified by a laboratory MMC test bench.
TL;DR: In this paper, a bi-layer compact thermal model with considering the three-dimensional heat spreading and thermal conduction for the junction temperature gradient prediction in microchannels with non-uniform heat source was presented.
01 Aug 2019
TL;DR: In this paper, a new method based on the on-state resistance was proposed to realize on-line junction temperature monitoring of silicon carbide (SiC) MOSFETs.
Abstract: Temperature estimation of MOSFET is crucial, for failure of semiconductors is closely related to the junction temperature. In order to improve the reliability of semiconductor devices, it is necessary to realize on-line temperature monitoring. However, it remains a challenge to measure the junction temperature fast and precisely, especially for high-switching-frequency devices, such as silicon carbide (SiC) MOSFET devices. To realize on-line junction temperature monitoring of SiC MOSFETs, this paper proposes a new method based on the on-state resistance. Firstly, on-state resistance is proven theoretically to be an available thermo-sensitive electrical parameter (TSEP). Then, a circuit with an auxiliary MOSFET is proposed to measure the on-state voltage drop online. It can provide accurate on-state voltage measurement, while working at higher frequencies with lower power consumption. Finally, the off-line and on-line experiment results demonstrate that the proposed method has a relatively satisfactory performance of monitoring the junction temperature of SiC MOSFETs online.