Showing papers on "Junction temperature published in 2020"

Nanoscale electro-thermal interactions in AlGaN/GaN high electron mobility transistors

Abstract: Self-heating in AlGaN/GaN high electron mobility transistors (HEMTs) negatively impacts device performance and reliability. Under nominal operating conditions, a hot-spot in the device channel develops under the drain side corner of the gate due to a concentration of volumetric heat generation leading to nonequilibrium carrier interactions and non-Fourier heat conduction. These subcontinuum effects obscure identification of the most salient processes impacting heating. In response, we examine self-heating in GaN-on-Si HEMTs via measurements of channel temperature using above-bandgap UV thermoreflectance imaging in combination with fully coupled electrothermal modeling. The methods together highlight the interplay of heat concentration and subcontinuum thermal transport showing that channel temperature cannot be determined solely by continuum scale heat transfer principles. Under conditions of equal power dissipation (PDISS = VDS × IDS = 250 mW), for example, a higher VDS bias (∼23 V) resulted in an ∼44% larger rise in peak junction temperature compared to that for a lower VDS (∼7.5 V) condition. The difference arises primarily due to reduction in the heat generating volume when operating under partially pinched-off (i.e., high VDS) conditions. Self-heating amplifies with this reduction as heating now takes place primarily over length scales less than the mean free path of the phonons tasked with energy dissipation. Being less efficient, the subcontinuum transport restricts thermal transport away from the device hot-spot causing a net increase in channel temperature. Taken together, even purely thermally driven device mean-time-to-failure is not, therefore, based on power dissipation alone as both bias dependence and subcontinuum thermal transport influence device lifetime.

Effect of Asymmetric Layout and Unequal Junction Temperature on Current Sharing of Paralleled SiC MOSFETs With Kelvin-Source Connection

Abstract: Parallel connection of silicon carbide (SiC) mosfet s is a popular solution for high-capacity applications. In order to improve the switching speed of paralleled SiC mosfet s, Kelvin-source connection is widely employed. However, the influences of asymmetric layout and unequal junction temperature on current sharing of paralleled SiC mosfet s with Kelvin-source connection are not clear. This article addresses the issue for the first time by theoretical analysis and experimental verifications. The mechanism of current imbalance resulting from asymmetric layout and unequal junction temperature in the case with Kelvin-source connection is comprehensively investigated. Then, some significant discoveries are obtained. The static current sharing performance can be affected by drain and power source parasitic inductance, which is seldom mentioned before. Besides, this article first points out that the effect of power source parasitic inductance on dynamic current sharing is dominant compared with other parasitic inductance. What is more, the thermal–electric analyzing results suggest that there is a risk of thermal runaway for paralleled SiC mosfet s with Kelvin-source connection at high switching frequency due to positively temperature-dependent dynamic current and switching losses. Based on the discoveries, some guidelines are provided for layout design and application of paralleled SiC mosfet s with Kelvin-source connection.

Lifting-Off of Al Bonding Wires in IGBT Modules Under Power Cycling: Failure Mechanism and Lifetime Model

Abstract: Lifting-off of Al bonding wires is one common failure mode of insulated-gate bipolar transistor (IGBT) modules during long-time operation. In the present work, the failure mechanism of Al wires lifting-off was investigated and the major factors were discussed based on both experiments and finite element (FE) simulations. It indicates that lifting-off of Al-wires is mainly determined by the interfacial thermal stress at the bonding interface. Thermal expansion of Al-wires and thermal mismatch of Al–Si interfaces contribute to the interfacial thermal stress which is affected by the resistance heat of Al-wires and power loss of Si-chips. Accordingly, a new lifetime model for the Al wires lifting-off failure mode of IGBT modules is proposed and verified through power cycling tests. The conduction current $I_{c}$ , the heating time $t_{\mathrm{\scriptscriptstyle ON}}$ , and the junction temperature swing $\Delta T_{j}$ are three major factors for the fatigue life model of IGBTs under Al wires lifting-off failure mode.

Modeling and analysis for thermal management in gallium oxide field-effect transistors

Abstract: Increased attention has been paid to the thermal management of β-Ga2O3 devices as a result of the large thermal resistance that can present itself in part due to its low intrinsic thermal conductivity. A number of die-level thermal management approaches exist that could be viable for thermal management. However, they have not been assessed for β-Ga2O3 devices exclusively. Here, we explore the limits of various die level thermal management schemes on a β-Ga2O3 metal–semiconductor field-effect transistor using numerical simulations. The effects of the various cooling approaches on the device channel temperature were comprehensively investigated, along with guidance for material selection to enable the most effective thermal solutions. Among various cooling strategies, double side cooling combined with a heat spreader used in the active region of the device can suppress the device thermal resistance to as low as 11 mm °C/W, achieving a maximum dissipated power density as high as 16 W/mm for a junction temperature limit of 200 °C. A multi-finger transistor thermal model was also developed to assess the potential of β-Ga2O3 devices for higher output power applications. Overall, this numerical study shows that it is possible to achieve high power β-Ga2O3 device operation with appropriate die-level thermal management solutions.

In situ Degradation Monitoring of SiC MOSFET Based on Switching Transient Measurement

Abstract: This paper presents an silicon carbide (SiC) MOSFET health condition monitoring method based on the switching transient measurements. Specifically, the device's turn -on time is used as the aging precursor, and a detection circuit is developed with picosecond resolution to detect the variations of the turn -on time. For this purpose, power cycles with constant junction temperature swings are applied on sample devices to accelerate their thermally triggered degradation. Over the aging process, device parameters are measured periodically using automated curve tracer to observe degradation-related changes. Also, a double pulse tester is used to evaluate devices’ switching transient changes throughout aging. Based on these results, both the theoretical discussions and experimental results imply that device turn -on time is a viable aging precursor and can be used to monitor device health at system start-up. High-resolution capture module of readily available system microcontroller is employed to measure the turn -on time through a simple auxiliary interface circuit on a buck converter. Experimental results show that onboard device aging can successfully be achieved during systems start-up in the order of microseconds.

Thermal Modeling and Design Optimization of PCB Vias and Pads

Abstract: Miniature power semiconductor devices mounted on printed circuit boards (PCBs) are normally cooled by means of PCB vias, copper pads, and/or heatsinks. Various reference PCB thermal designs have been provided by semiconductor manufacturers and researchers. However, the recommendations are not optimal, and there are some discrepancies among them, which may confuse electrical engineers. This paper aims to develop analytical thermal resistance models for PCB vias and pads, and further to obtain the optimal design for thermal resistance minimization. First, the PCB via array is thermally modeled in terms of multiple design parameters. A systematic parametric analysis leads to an optimal trajectory for the via diameter at different PCB specifications. Then, an axisymmetric thermal resistance model is developed for PCB thermal pads where the heat conduction, convection, and radiation all exist; due to the interdependence between the conductive/radiative heat transfer coefficients and the board temperatures, an algorithm is proposed to fast obtain the board-ambient thermal resistance and to predict the semiconductor junction temperature. Finally, the proposed thermal models and design optimization algorithms are verified by computational fluid dynamics simulations and experimental measurements.

Power Loss Model and Device Sizing Optimization of Si/SiC Hybrid Switches

Abstract: Si/SiC hybrid switches of parallel Si insulated-gate bipolar transistor (IGBT) and SiC metal–oxide–semiconductor field-effect transistor ( mosfet ) offer most of the SiC benefits but at a much lower cost in comparison to a full SiC solution. The hybrid switch can be optimized to achieve a minimum total power loss while utilizing the smallest SiC chip size without exceeding the specified maximum junction temperature. In this article, we first develop a generalized power loss model for Si/SiC hybrid switches with total power loss and junction temperature as outputs and SiC device size as a continuous input variable, and then develop a methodology to minimize SiC device size while optimizing total IGBT/ mosfet power loss and ensuring maximum junction temperature still below 150 °C. The power loss model is experimentally validated through both simple double pulse testing and a dc–dc buck converter case study. Using the model and optimization methodology, a minimum SiC device size can be obtained with optimized power loss and safe operation temperature.

Active Gate Delay Time Control of Si/SiC Hybrid Switch for Junction Temperature Balance Over a Wide Power Range

Abstract: The optimal gate delay time control between the two internal devices to achieve excellent electrical and thermal performance of the Si/SiC hybrid switch is considerably affected by several factors and requires careful adjustment to suit the different operation conditions of power converters. However, the conventional gate control solution for the hybrid switch applies a fixed delay time to achieve the minimum switching loss at a specific load current, resulting in disparities in junction temperature of internal devices over a wide load range. This effectively reduces the safe operating area by risking one internal switch subjected to overrated junction temperature in a wide range operation with regard to power handling condition. To avoid such a serious risk of reliability degradation or thermal breakdown, a novel active gate delay time control strategy based on the electro-thermal coupling loss model is proposed. The gate delay time was dynamically adjusted and optimized according to the operation conditions of power converters so that the operation junction temperature difference of the two internal devices can be minimized. Experimental results demonstrate that the junction temperature of the hybrid switch decreases by 20 °C at 8-kW load condition and its maximum power handling capability increases by 18%, without compromising the power converter's efficiency in a 20 kHz Si/SiC hybrid switch-based dc/dc buck converter compared with the conventional approach.

Modified Phase-Shifted PWM Scheme for Reliability Improvement in Cascaded H-Bridge Multilevel Inverters

Abstract: The cascaded H-bridge multilevel inverter (CHMI) is a modular structure that consists of many power semiconductor switches. With this increase in the number of power semiconductor switches, it is hard to predict and handle the failure of the devices, and hence reliability of CHMI decreases. The major cause of power semiconductor switch failure is junction temperature that is produced by power losses. The study proposes a multi-carrier pulse-width modulation (PWM) scheme for reduction in switching losses of CHMI. In the proposed modulation scheme, the two legs conduct switching operation at different frequencies for switching reduction. One leg conducts switching operation with high frequency, while the other leg conducts switching operation with fundamental frequency. The switching operations with different frequencies cause unbalanced switching loss to each leg. Therefore, the junction temperature that is based on power losses leads to different life-times for the power semiconductor switch. Additionally, the switching frequency of the two legs is alternated to evenly distribute switching losses and junction temperature. Simulation and experimental results verify the performance of the proposed PWM scheme.

Accurate Computation of IGBT Junction Temperature in PLECS

Abstract: In the article, a new method to improve the accuracy of the insulated-gate bipolar transistor (IGBT) junction temperature computations in the piecewise linear electrical circuit simulation (PLECS) software is proposed and described in detail. This method allows computing the IGBT junction temperature using a nonlinear compact thermal model of this device in PLECS. In the method, a nonlinear compact thermal model of the IGBT is used, which considers the dependence of thermal resistance on the junction temperature. The usefulness of the method is experimentally verified, and it is confirmed that it increases the accuracy of the computations and shortens their time. The differences between the measured and computed characteristics are discussed. The application of the developed method for computations resulted in a significant reduction of their error to only a few percent. The developed method can be applied in the system-level simulations of the power electronics converters.

Study of Current Density Influence on Bond Wire Degradation Rate in SiC MOSFET Modules

Abstract: This paper proposes a separated test method for studying the current effect on the ageing process of a wire-bonded silicon carbide (SiC) MOSFET module under power cycling test (PCT). The separated test method enables testing SiC MOSFET at different load current densities, but under the same temperature swing and average temperature conditions. By analyzing the output characteristics in the linear region, the relationships among the gate voltage, on-state voltage, and junction temperature are revealed. Then, the one-to-one correspondence between gate voltage and conduction power loss can be used to adjust the current density under the same temperature conditions. Two six-pack SiC modules (1200 V/20 A) are tested under 12 and 24 A conditions to experimentally verify the proposed method. The ageing curves show that the high current can speed up the ageing rate of bond wires even under the same temperature conditions (65 °C–125 °C). Moreover, the high current density also has an impact on solder layer degradation as well as on the temperature conditions. Finally, a power device analyzer B1506A and a scanning acoustic microscope (SAM) are used to investigate the degradation of electrical parameters and the solder layer, respectively. The final summary of analytical results shows that the input current has a nonnegligible impact on the degradation process of power modules.

Electroluminescence-Based Junction Temperature Measurement Approach for SiC Power MOSFETs

Abstract: The measurement of the junction temperature of power semiconductor devices during operation is highly relevant for efficient power electronic applications. This paper presents a novel galvanic isolated sensing approach for the online junction temperature measurement of a silicon carbide (SiC) mosfet . It is based on the temperature-dependent changes in the spectrum of the light emission from the body diode of the SiC mosfet . The spectrum exhibits two characteristic peaks at roughly 380 nm and around 480 nm. The first peak's intensity increases with rising temperature, whereas the other decreases. Consequently, the junction temperature can be derived from the ratio of the filtered intensities of those two wavelength regions. The proposed method is studied on the basis of a virtual experiment and experimentally validated by means of static characterization and dynamic double pulse measurement.

Reliability Enhancement of a Power Semiconductor With Optimized Solder Layer Thickness

Abstract: This article deals with the reliability of a power semiconductor exposing to the severe thermal stresses. The importance of solder joint thickness on the power semiconductor's useful lifetime is demonstrated in this article. Solder layer thickness has knock on effects both on the creep accumulated strain and thermal characteristics of the power semiconductors. Since, these effects are in contradictory of each other, a trade-off seems to be essential to optimize the solder layer thickness. Thereby, thermo-mechanical behavior of a discrete power semiconductor under the thermal mission profile was simulated and the results were integrated to the actual conditions. The simulation results reveal that after thermal cycling, some creep strain is produced in the solder layer especially at the corners. The thinner the solder joint was, the greater accumulated creep strain was observed leading to the faster degradation. On the contrary, the thicker the solder layer was, the larger thermal resistance was observed leading to the higher junction temperature. Accordingly, the article is concentrated on optimizing the solder layer thickness based on these two issues. The scanning electron microscope micrographs, the EDS maps and X-ray diffraction analysis were also taken to indicate the solder layer thickness effects on the number of voids and their propagations in the different solder layer thicknesses. The experimental tests validate the expected results in the extracted simulations.

Thermal Stress Balancing Oriented Model Predictive Control of Modular Multilevel Switching Power Amplifier

Abstract: Power amplifiers have a wide range of applications in civilian and military areas. In this article, a modular multilevel switching power amplifier (MMSPA) with high power and high output performance is investigated. Due to mismatched parameters or proper control signals among the modules, there may be significant temperature differences among the modules of MMSPA under long-term operations. Uneven temperatures among modules directly lead to premature aging and failure, which in turn affects the overall system reliability. Aiming at the thermal stress imbalance among modules of MMSPA, a model predictive control based on the thermal stress balance is proposed. First, the mathematical model is constructed for the MMSPA. Then, the junction temperature estimation method based on the power loss calculation is presented. On this basis, the finite set control switch state optimization and the switch distribution algorithm for thermal balance are presented. Finally, the proposed active thermal control is verified by the simulation and the experimental results.

High-Temperature Characterization of a 1.2-kV SiC MOSFET Using Dynamic Short-Circuit Measurement Technique

Abstract: Threshold voltage and channel mobility of a 1.2-kV planar-channel SiC MOSFET at high junction temperature ( $T_{j}$ ) up to 700 °C have been extracted and analyzed for the first time, by virtue of a specially designed short-circuit (SC) measurement technique we developed. Under the SC condition, $T_{j}$ of the SiC MOSFET can rise significantly within a few microseconds, which can be extracted based on the SC waveforms and thermal calculations. The planar-channel SiC MOSFET investigated in this work can maintain normally-off operation at an elevated $T_{j}$ up to 700 °C. Furthermore, the underlying mechanisms of the temperature dependence of the threshold voltage and channel mobility are also analyzed. The threshold voltage of the SiC MOSFET exhibits a different temperature dependence over a wide range (120–700 °C) compared with that of Si counterparts, which is attributed to interface traps’ response. The channel mobility shows a non-monotonic temperature dependence, due to divergent scattering mechanisms.

Enhancement of Hot Spot Cooling by Capped Diamond Layer Deposition for Multifinger AlGaN/GaN HEMTs

Abstract: The impact of a capped diamond layer for enhanced cooling of multifinger AlGaN/GaN high-electron-mobility transistors (HEMTs) has been investigated under the steady-state operating condition. By depositing a capped diamond thin film onto the HEMTs, the temperature distribution around the hot spots tends to be more uniform and the junction temperature can be suppressed significantly. The capped diamond serves as a highly effective heat spreader, and its thermal spreading ability depends on the structural design patterns and working conditions. Some key parameters affecting the thermal performance of the capped diamond have been examined, including the heat dissipation power density, gate pitch distance, embedding depth of the heat source, thermal boundary resistance, substrate material, as well as the cap thickness. For the 12-finger model with 20- $\mu \text{m}$ gate pitch distance and gate power density of 6 W/mm, a 20- $\mu \text{m}$ layer of capped diamond could reduce the junction temperature by 12.1% for GaN-on-diamond HEMTs and by 25.3% for GaN-on-SiC HEMTs. Even with a 1- $\mu \text{m}$ capped diamond layer, the reduction would be 7.6% and 9.9%, respectively. The temperature reduction for GaN-on-Si is more significant.

Active Thermal Control for Hybrid Modular Multilevel Converter Under Overmodulation Operation

Abstract: The thermal management plays an important role in improving the reliability and lifetime of high power converters, especially for the high voltage direct current (HVdc) transmission system. In the voltage source converter based HVdc systems (VSC-HVdc), the hybrid modular multilevel converters (MMCs) are taken as the excellent candidates due to their dc short-circuit fault ride-through ability and less submodule (SM) devices. Furthermore, the voltage modulation index of hybrid MMCs can be promoted to achieve higher power rating and efficiency. However, in this article, it is revealed that thermal stress distribution inside the SMs becomes more unbalanced under a high voltage modulation index, which would lead to serious thermal fatigue. To overcome this problem, the active bypass with thyristor for half-bridge submodules (HBSMs) and symmetrical modulation for full-bridge submodules (FBSMs) based active thermal control strategies are employed. With the presented thermal control strategies, the junction temperature of the most stressed devices in both HBSMs and FBSMs is reduced enormously. Besides, the thermal control strategy does not bring negative influence on the steady-state output performance of hybrid MMC. Finally, the theoretical analysis and effectiveness of the proposed control methods are verified based on a laboratorial MMC prototype.

Estimating Junction Temperature of SiC MOSFET Using Its Drain Current During Turn-On Transient

Abstract: Silicon carbide metal–oxide–semiconductor field-effect transistor (SiC MOSFET) has become a promising device due to its excellent material properties. Junction temperature is an important parameter and a significant health index. In this article, drain current during turn-on transient is taken as the thermo-sensitive electrical parameter (TSEP) to monitor the junction temperature of SiC MOSFET. Based on the physical properties of wide bandgap semiconductor materials, the switching behaviors of SiC MOSFET and the variation of drain current with temperature were studied. The influence of temperature dependence of threshold voltage and carrier mobility on drain current is analyzed. It is proven that the drain current has a positive temperature coefficient during turn-on transient. Finally, the validity of the proposed method is verified by the theoretical analysis and experiments.

Comparative Analysis of IGBT Parameters Variation Under Different Accelerated Aging Tests

Abstract: Power semiconductor devices are vulnerable to thermomechanical fatigue due to temperature cycling caused by system load profile and external climatic conditions. As the reliability performance of power semiconductor devices in power converter systems is determined by this temperature stress, accelerated power or thermal cycling test are used in this article to emulate the temperature stress. The failure mechanisms due to temperature stress can be studied, and it also helps to develop the lifetime estimation model for power semiconductor devices. In the past, active power cycling and passive thermal cycling tests are investigated separately to develop the failure mechanism model based on the device’s electrical parameter changes and scanning electron microscopic (SEM) analysis. However, there is no detailed report on, how different temperature stresses emulated by dc, pulsewidth modulation (PWM) power cycling, and thermal cycling affects the device physically, and how much changes it introduces in the device’s electrical parameters. Therefore, this article presents an experimental investigation of active dc, PWM power cycling and passive thermal cycling approaches on 1.2-kV 50-A fast trench insulated gate bipolar junction transistor (IGBT) devices. The device electrical parameters, such as ON-state voltage, threshold voltage, gate current, gate voltage, and thermal resistance, were monitored during the study to classify the effects of temperature stress produced by dc, PWM power cycling, and thermal cycling on these electrical parameters.

Thermal Performance and Reliability Analysis of a Medium-Voltage Three-Phase Inverter Considering the Influence of High $dv/dt$ on Parasitic Filter Elements

Abstract: In recent years, the use of silicon carbide (SiC) power semiconductor devices in medium-voltage (MV) applications has been made possible due to the development of high blocking voltage (10–15 kV)-based devices. While the use of these devices brings in a lot of advantages, the semiconductor devices are exposed to high peak stress (of up to 15 kV) and a very high $dv/dt$ (of up to 100 kV/ $\mu \text{s}$ ). The high $dv/dt$ across the devices leads to a high $dv/dt$ across other components connected to the system. This makes the effect of the parasitic capacitance across the components to be of paramount importance since an additional current flows through the components and, consequently, through the switching device. This additional current flows during each switching transition and leads to increased switching losses in the device. This article analyzes the effect of these additional losses on the lifetime of the device. The thermal performance of a three-phase inverter power block is provided, and a mission profile (solar irradiance and temperature)-based analysis is carried out to account for the additional junction temperature rise. The rainflow counting method is implemented to identify the mean and amplitude of each thermal cycle. An empirical device lifetime model is used to calculate the number of cycles to failure. Finally, the Palgrem Miner rule is used to quantify the total damage in the device. Comparisons have been carried out on basis of lifetime for both the cases (with and without the influence of parasitic capacitances). This analysis can be helpful in validating the importance of the design of filter inductors in these MV applications.

Utilizing Electroluminescence of SiC MOSFETs for Unified Junction-Temperature and Current Sensing

Abstract: This work proposes a method for unified junction-temperature and device-current sensing that utilizes the body-diode electroluminescence of SiC MOSFETs. During conduction, the body diode of SiC MOSFETs emits light in the visible spectrum that is dependent on the device current and junction temperature. The sensing of this light offers the potential for a galvanically isolated and high-bandwidth junction-temperature and device-current measurement. Previous publications successfully showed that either temperature or current information can be extracted from the intensity of the emitted light if the other variable is known. However, they did not aim to independently extract the two variables. This work presents a unique extraction method that separately extracts device current and junction temperature by using intensity and wavelength information of the body-diode electroluminescence. The decoupled device-current and junction-temperature extraction works on the basis of multiple optical sensors with different wavelength sensitivities and artificial-intelligence techniques. This method is demonstrated via experimental evaluations using an automotive-grade SiC power module. Its integration in next generation power modules enables high-performance electrothermal monitoring for safe and reliable long-term operation.

A High Precision On-Line Detection Method for IGBT Junction Temperature Based on Stepwise Regression Algorithm

Abstract: The insulated gate bipolar transistor (IGBT), one of the most vulnerable component, is one of the most precious central component in the converter interior. High junction temperature will lead to device failure, which is the main reason of failure of power electronic system. Therefore, on-line high precision measurement of IGBT module junction temperature is the basis of life prediction and reliability evaluation of high-power power conversion equipment. In this paper, the principle of IGBT junction temperature extraction and the latest development of related technologies are summarized. In particular, the working principle and shortcomings of temperature sensitive electrical parameter (TSEP) method are summarized. The change of junction temperature will affect the inter-electrode capacitance in the internal structure of IGBT, which will cause the change of temperature sensitive electrical parameters. The single temperature sensitive electrical parameter method is easily affected by IGBT structure and inter-electrode capacitance. This paper presents an algorithm for high precision on-line detection of IGBT junction temperature. The parameter types are optimized by stepwise regression and the model is established accordingly. In this paper, IGBT: FF50R12RT4 is used as the experimental equipment. By comparing the junction temperature model established based on multiple linear stepwise regression algorithm with the junction temperature model based on traditional temperature sensitive electrical parameters, it is proved that the algorithm has better fitting degree and precision, and the algorithm can be used for high precision online extraction of junction temperature.

Microchannel Thermal Management System With Two-Phase Flow for Power Electronics Over 500 W/cm 2 Heat Dissipation

Abstract: In this article, a microchannel thermal management system (MTMS) with the two-phase flow using the refrigerant R1234yf with low global warming potential is presented. The thermal test vehicles (TTVs) were made of either single or multiple thermal test chips embedded in the substrates, which were then attached to the MTMS. The system included two identical aluminum microchannel heat sinks (MHSs) connected in series in the cooling loop, which also consisted of a gas flowmeter, a miniature compressor, a condenser, a throttling device, and accessory measurement components. The experimental results showed that the thermal management system could dissipate a heat flux of 526 W/cm2 while maintaining the junction temperature below 120 °C. For SiC mosfet with a higher junction temperature, e.g., 175 °C, the current system is expected to dissipate a heat flux as high as about 750 W/cm2. The effects of the rotational speed of the compressor, the opening of the throttling device, TTV layout on MHS, and a downstream heater on the cooling performance of the system were analyzed in detail. The study shows that the present thermal management with a two-phase flow system is a promising cooling technology for the high heat flux SiC devices.

Influence of PWM Methods on Semiconductor Losses and Thermal Cycling of 15-kVA Three-Phase SiC Inverter for Aircraft Applications

Abstract: This paper presents the influence of different pulse width modulation (PWM) methods on losses and thermal stresses in SiC power modules used in a three-phase inverter. The variation of PWM methods directly impacts instantaneous losses on these semiconductors, consequently resulting in junction temperature swing at the fundamental frequency of the converter’s output current. This thermal cycling can significantly reduce the lifetime of these components. In order to determine semiconductor losses, one needs to characterize SiC devices to calculate the instantaneous power. The characterization methodology of the devices, the calculation of instantaneous power and temperature of SiC dies, and the influence of the different PWM methods are presented. A 15-kVA inverter is built in order to obtain experimental results to confirm the characterization and loss calculation, and we show the best PWM methods to increase efficiency and reliability of the three-phase inverter for specific aircraft applications.

Optical and frequency degradation behavior of GaN-based micro-LEDs for visible light communication.

Abstract: In this study, optical power and frequency response degradation behavior of GaN-based micro-LEDs with bandwidth up to 800MHz were investigated under different modes, including direct current (DC) mode, alternating current (AC) mode and DC plus AC small signal mode at room temperature. The electroluminescence (EL), current-voltage (I-V) characteristics and small signal frequency response were measured during the stress. The results show that micro-LEDs under AC mode have better reliability because of the decreased junction temperature, but the high current density would still generate some defects within or around the active region, which can increase the trap-assisted tunneling (TAT) current and non-radiative recombination. The electrical stress-related defects not only reduce the effective carrier concentration injected into QWs but also increase the carrier lifetime for radiative recombination and Auger recombination and decrease the modulation bandwidth. These results will help to understand and improve the reliability of micro-LEDs operated under high current density and promote the application of micro-LEDs for visible light communication.

Electrothermal-Based Junction Temperature Estimation Model for Converter of Switched Reluctance Motor Drive System

Abstract: In this paper, an electrothermal-based junction temperature estimation model is proposed for an asymmetric half-bridge converter of a switched reluctance motor drive system. In the current chopping control mode, there exists a particularly uneven temperature distribution on converters due to not only the thermal coupling effects and dissipating boundary conditions, but also the different device losses in the same phase bridge. For the purpose of precise estimation for junction temperature, first, the power loss of converter is accurately calculated by the interpolation method with the help of Simulink and LTspice. Second, the thermal coupling effects and dissipating boundary conditions are analyzed in the three-dimensional finite-element method (FEM) model. According to the step power response extraction, a coupling impedance matrix is used to describe the nonnegligible thermal coupling effects between devices, and the complete heatsink can be decoupled into multiple subdivisions that represent the different heat dissipating boundary conditions. Then, with coupling impedances and subheatsink impedances in series, a compact RC network model can be built for junction temperature estimation. Consequently, analytical investigation in conjunction with FEM simulation and experiment measurements demonstrate the validity of the proposed model.