Showing papers on "Junction temperature published in 2021"
TL;DR: Wang et al. as mentioned in this paper proposed a new cooling concept enabled by a compact loop heat pipe module, which can provide high reliability operation, meanwhile maintaining high thermal performance, and demonstrated that the 4-mm thick loop heatpipe module with finned tube condenser could dissipate a heat load of 150-W under a wide fan voltage range from 12-V to 24-V at tested directions when the chip junction temperature was below 85°C.
46 citations
22 Apr 2021
TL;DR: In this paper, the authors presented the application of wide bandgap (WBG) semiconductor devices with cryogenic cooling and demonstrated the feasibility of operating high-power SiC converter with Cryogenic cooling.
Abstract: This article presents the cryogenically cooled application for wide bandgap (WBG) semiconductor devices. Characteristics of silicon carbide (SiC) and gallium nitride (GaN) at cryogenic temperatures are illustrated. SiC MOSFETs exhibit increased on-state resistance and slower switching speed at cryogenic temperatures. However, cryogenic cooling provides low ambient temperature environment and thus enables the SiC converter to operate at lower junction temperature to achieve higher efficiency compared to room temperature cooling. A cryogenically cooled MW-level SiC inverter prototype is developed and demonstrated the feasibility of operating high-power SiC converter with cryogenic cooling. GaN HEMTs exhibit more than five times on-state resistance reduction and faster switching speed at cryogenic temperatures which makes GaN HEMTs an excellent candidate for cryogenic power electronics applications. The significantly reduced on-state resistance of GaN devices provides the possibility to operate them at a current level much higher than rated current at cryogenic temperatures. A GaN double pulse test (DPT) circuit is constructed and demonstrated that GaN HEMTs can operate at nearly four times of rated current at cryogenic temperatures. Challenges of utilizing WBG device with cryogenic cooling are discussed and summarized.
43 citations
TL;DR: In this paper, a novel online IGBT junction temperature measurement method based on the on-state voltage drop is proposed, which can monitor the voltage drop of the IGBT and extract IGBT temperature online.
Abstract: Insulated gate bipolar transistor (IGBT) module is the most widely used power electronic device in converters. Condition monitoring of IGBT is critical for avoiding sudden failures. Health management of converters based on accurate IGBT junction temperature is of great importance to reliable operation. However, the existing monitoring methods have some drawbacks, including low feasibility of online implementation, intrusiveness, and slow response. IGBT junction temperature has a strong influence on IGBT on -state voltage drop. A novel online IGBT junction temperature measurement method based on the on -state voltage drop is proposed in this article. This technique can monitor the on -state voltage drop of IGBT and extract IGBT junction temperature online. Besides, the influences of the measurement circuit temperature variations and IGBT load current variations are considered and compensated based on the off -state stage of the IGBT. Simulation and experimental results validate the feasibility of the proposed technique. The proposed method has advantages of fast response, low cost, and simple circuit structure for noninvasive online IGBT junction temperature monitoring.
37 citations
TL;DR: In this paper, a potential approach for the junction temperature estimation of SiC MOSFETs based on the dynamic threshold voltage was proposed, which is independent of load current variation, which eliminates the complicated calibration procedure with load current.
Abstract: The online junction temperature monitoring of power devices is a viable technique to ensure the reliable operation of mission-critical power electronic converters. This article provides a potential approach for the junction temperature estimation of SiC MOSFET s based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with load current. First, the physical mechanism and the temperature dependence of the dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of the dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double-pulse tests. The experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of the dynamic threshold voltage of two SiC MOSFET s is approximately 5.2 mV/°C and 19.6 mV/°C, respectively.
36 citations
TL;DR: In this paper, a model based on the first and second laws of thermodynamics is developed in MATLAB R2020a Simulink software and is utilized in thermodynamically optimizing a bismuth telluride based solar thermoelectric generator (STEG) while estimating all system irreversibilities.
32 citations
TL;DR: In this article, a graphite-embedded insulated metal substrate (thermally-annealed-pyrolytic-graphite embeddings) was proposed for widebandgap power modules.
Abstract: Emerging wide-bandgap (WBG) semiconductor devices such as silicon carbide (SiC) metal–oxide semiconductor field-effect transistors (MOSFETs) and gallium nitride high-electron-mobility transistors can handle high power in reduced semiconductor areas better than conventional Si-based devices owing to superior material properties. With increased power loss density in a WBG-based converter and reduced die size in power modules, thermal management of power devices must be optimized for high performance. This article presents a graphite-embedded insulated metal substrate (thermally-annealed-pyrolytic-graphite-embedded insulated metal substrate—IMSwTPG) designed for WBG power modules. Theoretical thermal performance analysis of graphite-embedded metal cores is presented, with design details for IMSwTPG with embedded graphite to replace a direct-bonded copper (DBC) substrate. The proposed IMSwTPG is compared with an aluminum nitride-based DBC substrate using finite-element thermal analysis for steady-state and transient thermal performance. The solutions’ thermal performances are compared under different coolant temperature and thermal loading conditions, and the proposed substrate's electrical performance is validated with static and dynamic characterization. Using graphite-embedded substrates, junction-to-case thermal resistance of SiC MOSFETs can be reduced up to 17%, and device current density can be increased by 10%, regardless of the thermal management strategy used to cool the substrate. Reduced transient thermal impedance of up to 40% of dies owing to increased heat capacity is validated in transient thermal simulations and experiments. The half-bridge power module's electrical performance is evaluated for on -state resistance, switching performance, and switching loss at three junction temperature conditions. The proposed substrate solution has minimal impact on conduction and switching performance of SiC MOSFETs.
29 citations
TL;DR: A highly modular, integrated, and compact drive is achieved compared to the nonintegrated version, and an experimental setup is built to validate the results of the introduced multiphysics models.
Abstract: In this article, a circumscribing polygon integrated modular motor drive topology with shared cooling for the power converter and the electrical machine is proposed and benchmarked with the nonintegrated version. The proposed topology is applied on an axial flux permanent magnet synchronous machine. The topology is capable of mechanically mounting the power converter, sufficiently cooling both the power converter and the electrical machine, and combining both of them into the same housing. The mechanical and the thermal design are done to ensure thermal decoupling between the power converter and the motor winding, and to provide a low thermal resistance from the power converter and the electrical machine to the ambient. Due to the limited space available for the power converter module, wide bandgap semiconductor technology is chosen for the implementation of the converter module, thanks to their small package size and low power losses. A highly modular, integrated, and compact drive is achieved compared to the nonintegrated one. A computational fluid dynamics (CFD) model is developed for one module of the proposed integrated drive to evaluate the maximum current that can be injected by one converter module without exceeding the junction temperature limit of the switches and the maximum winding temperature. An experimental setup is built to validate the results of the introduced multiphysics models.
29 citations
TL;DR: A three-dimensional compact thermal network model that considers the thermal boundary conditions and can be obtained by the finite-element method (FEM), and a novel two-step method for thermal parameter extraction is presented.
Abstract: With the development of power electronics technology, power modules delivery considerably greater power density, which makes junction temperature an important parameter for reliable operation. Existing thermal models often ignore the influence of the thermal boundary conditions on the thermal parameter and cannot accurately predict junction temperature in various operating conditions. This article proposes a three-dimensional compact thermal network model that considers the thermal boundary conditions and can be obtained by the finite-element method (FEM). A novel two-step method for thermal parameter extraction is presented and the effects of boundary conditions on thermal network parameters are discussed in detail. The experimental results and FEM simulation show that the proposed thermal network model can accurately estimate the junction temperature in different thermal boundary conditions.
28 citations
TL;DR: In this paper, a method using time duration of the gate charge is proposed to monitor bond wires fatigue of the multichip IGBT modules when the modules are in the off-state.
Abstract: Monitoring the defective multichip insulated gate bipolar transistor (IGBT) module is a cost-effective approach to improve the quality of customer service A method using time duration of the gate charge is proposed to monitor bond wires fatigue of the multichip IGBT modules when the modules are in the off -state It is based on the fact that failure of the chip branch due to bond wires fatigue changes the gate input capacitance of the multichip IGBT module The health state of bond wires can be converted into the change of time duration of gate charge under the constant gate current A driver containing the constant current source is proposed The study results indicate that the time duration of the gate charge decreases significantly when the failure of the chip branch occurs, and the effect of junction temperature can be ignored within the special range of gate voltage Condition monitoring can be implemented during the off -state of the multichip module and without considering the effects of junction temperature The confirmatory experiment is carried out to verify the correctness of the proposed method
27 citations
TL;DR: A novel in situ IGBT junction temperature estimation method via turn-off collector voltage overshoot is proposed, which is independent on bond wire degradation and high resolution for online temperature estimation.
Abstract: Fast and accurate online monitoring of junction temperature of insulated gate bipolar transistor (IGBT) chips is of great significance for overtemperature protection and thermal stress optimization of IGBTs. However, existing IGBT junction temperature estimation methods have drawbacks of dependence on bond wire degradation, low resolution, nonlinearity, and difficulty in online implementation. In this article, a novel in situ IGBT junction temperature estimation method via turn- off collector voltage overshoot is proposed, which is independent on bond wire degradation. Based on theoretical analysis, the turn- off collector voltage overshoot is approximately linear to the junction temperature. The peak value of the turn- off collector voltage can be extracted during operation. Experiments are conducted to verify the technique proposed. A linear relationship between collector voltage overshoot and IGBT junction temperature is revealed, which illustrates the validity of the proposed method. Besides, the operation parameters (bus voltage, load current, and temperature) are considered, and the calibration on operation parameter variations is discussed. At last, the proposed method is compared with a traditional IGBT junction temperature estimation method based on the on -state voltage drop. The advantages of the proposed method lie in its independence on bond wire degradation and high resolution for online temperature estimation.
24 citations
TL;DR: This article proposes an effective heat propagation path (EHPP)-based real-time adaptive thermal model for IGBT modules, where the EHPP is proposed to quantify the impact of substrate solder cracks on the heat propagation inside the IGBT module.
Abstract: The information of junction temperature is crucial for the operational management of insulated-gate bipolar transistor (IGBT) modules. In practice, the junction temperature is typically estimated by using an electrothermal model. IGBT modules are subject to various aging processes during operation, some of which, e.g., substrate solder crack, change the thermal impedance of the IGBT module. However, few works in the literature have included the aging effect on the online thermal behavior modeling of IGBT modules. This article proposes an effective heat propagation path (EHPP)-based real-time adaptive thermal model for IGBT modules, where the EHPP is proposed to quantify the impact of substrate solder cracks on the heat propagation inside the IGBT modules. A straightforward relationship between substrate solder crack and the degree of nonuniformity of case temperature distribution is established. This relationship is then used to approximate the EHPP of the IGBT module in different substrate solder health conditions in real time using the measured nonuniformity of case temperature distribution. Based on the change of the EHPP, the parameters of a thermal equivalent circuit (TEC) model, e.g., an improved Cauer-type TEC, are adjusted online and in real time to track the thermal behavior changes of the IGBT modules caused by substrate solder cracks, leading to a real-time substrate-solder-aging-adaptive thermal model. The proposed real-time adaptive thermal model is validated by simulation studies and experimental tests for a commercial IGBT module.
TL;DR: In this paper, a composite phase change material (PCM) made from a copper foam infused with a Field's metal eutectic alloy was used to achieve both high cooling and the ability to buffer transient temperature spikes.
TL;DR: In this article, a localized direct phase-change cooling strategy is applied and integrated with direct bonded copper in IGBT power module, which provides a new perspective in the compact and efficient design of power electric modules.
Abstract: In electric vehicles and hybrid electric vehicles, insulated-gate bipolar transistor (IGBT) power module trends to dissipate higher heat flux due to increased power rating and reduced package size. An inefficient cooling method will result in stringent thermal reliability problems. Therefore, there is a strong need for innovative and efficient cooling technologies in order to tackle these issues. In this article, a localized direct phase-change cooling strategy is applied and integrated with direct bonded copper in IGBT power module. Vapor chamber with light weight, high thermal conductivity, and even temperature uniformity replaces original copper baseplate. Layers of thermal grease and original cooling plate are removed, leading to a further reduction in thermal resistance. In order to evaluate the new module, a thermal model and an experiment were built to analyze temperature distribution in layers, junction temperature, temperature uniformity, and thermal resistance. Results indicate the integrated thermal management system outperforms traditional cooling solutions on the cooling capacity. Improvements on junction temperature, temperature uniformity, and total thermal resistance are 34.6%, 76.6%, and 41.6%, respectively. The results illustrate the potential of phase-change cooling by vapor chamber. It provides a new perspective in the compact and efficient design of power electric modules.
TL;DR: In this article, a low-profile and high power density packaging solution of a SiC power module with enhanced electrical and thermal performance is presented, where the design optimizations on layout, chip placement, and terminal structure are compatible with the conventional module fabrication processes.
Abstract: Silicon carbide (SiC) power devices possess many beneficial properties for power electronics applications, but commercial 62-mm SiC power module packages with the direct drop-in replacement of Si devices limit many benefits of these SiC power devices. To fully utilize the advantages of the SiC power devices, this article presents a low-profile and high power density packaging solution of a 62-mm 1200-V/300-A SiC power module with enhanced electrical and thermal performance. The design optimizations on layout, chip placement, and terminal structure are compatible with the conventional module fabrication processes. An increase of power density by threefold is achieved with a low-profile package by reducing the height of the terminal connectors. Moreover, lower voltage overshoots of gate–source and drain–source of the proposed module are demonstrated due to low inductance in both gate and power loops. Thermal simulations show that the proposed module has a lower peak junction temperature and a more balanced temperature distribution among paralleled devices. Finally, the commercial and fabricated modules are characterized experimentally under the same conditions. Both simulation and experimental results show that the gate and power loop inductances of the proposed module are reduced by 96% and 76%, respectively. Moreover, the total switching loss and drain–source voltage overshoot are reduced by 44% and 54%, respectively, at 300 A using a 2- $\Omega $ external gate resistor.
TL;DR: In this article, the authors systematically analyzes the fundamental principle and the key objective of these methods and discusses their limitations and potential, highlighting important challenges, such as thermal state variable extraction, nonlinear aging, and minimizing the impact on system operation.
Abstract: The trend towards integrating power electronic converters and pushing their device utilization towards physical limits puts the spotlight on the junction temperature of the devices. The physical limits of power density are directly tied to the maximum junction temperature and junction temperature cycles that are considered as root-cause of the aging and finally the failure of the device. Therefore, manipulating the junction temperature with smart control algorithms is a promising method to enhance the power density as well as the lifetime of future converter systems. To address these opportunities, recent research proposed methods that increase the overload capability, reduce thermal cycles, balance thermal stress and share thermal loading of power converters. This paper systematically analyzes the fundamental principle and the key objective of these methods and discusses their limitations and potential. Based on this discussion it highlights important challenges, such as thermal state variable extraction, nonlinear aging, and minimizing the impact on system operation. These challenges must be addressed by future research to make active thermal control a key enabler of smart power converter with superior power density and reliability.
TL;DR: In this paper, a gate model of SiC MOSFET is proposed, and based on this model, an I G-based junction temperature estimation technique is presented, which can be used in various types of power electronics devices.
Abstract: Junction temperature monitoring is the basis of high reliability for silicon carbide (SiC) devices since thermal stress is the dominating aging factor. Due to the high switching frequency, conventional thermal-sensitive electrical parameter (TSEP) methods have poor monitoring performance for SiC MOSFETs. The gate current I G has been found as an effective TSEP for SiC MOSFETs. However, the exact relationship between the I G and the junction temperature and its fundamental principle has not yet been fully revealed. Moreover, existing monitoring methods based on the I G are limited to specific devices and require a complex measuring system. In order to solve the problems above, this article puts forward a novel junction temperature monitoring method based on the I G. First, a gate model of SiC MOSFET is proposed. Second, based on this model, an I G-based junction temperature estimation technique is presented. Third, an online measuring method for the I G is proposed. Finally, online experiments validate the proposed method. This novel method has three advantages. First, it can be used in various types of power electronics devices. Second, it can provide decent precision in various working conditions. Third, the measurement circuit required by his method is simple, which adds no additional hardware.
TL;DR: A technique is proposed where the individual dies in a multidie power module can be selectively driven by a closely integrated gate buffer, and a profiling of the power loss within the intelligent power module is enabled.
Abstract: Due to practical limitations in the manufacturing of power semiconductor dies, high power modules are composed of several dies in parallel in order to meet the desired load current requirements. With careful attention to the design, modern insulated gate bipolar transistor (IGBT)-based power modules feature relatively balanced current distribution amongst the parallel dies. However, owing to the increased switching speeds of wide bandgap devices, i.e., silicon carbide (SiC), it is challenging to design the package to achieve both low-loss and balanced operation. In this article, a technique is proposed where the individual dies in a multidie power module can be selectively driven by a closely integrated gate buffer. Amongst the benefits achieved by selectively driving the die gates, a profiling of the power loss within the intelligent power module is enabled. Furthermore, a practical technique to estimate the individual die temperatures is presented, and using the same method, the on-state voltage of the power module during load current conduction can be estimated. Finally, it is experimentally demonstrated that the combination of individual junction temperature estimation and the selective gate driving can be used to increase the power density of the power module by better utilizing the component dies.
TL;DR: In this article, the effect of the operating conditions on the performance of passive electronic thermal management systems based on phase change materials is explained, and the main outcome is that the use of the enhanced surface does not always lead to an improvement of the heat transfer performance especially during fast intermittent operations and thus the maximum effective thermal conductivity cannot always be considered the main design objective.
TL;DR: In this article, a temperature-dependent Cauer-type thermal model of the SiC MOSFET is proposed and extracted based on offline finite-element simulations, and the experimental measurement of transient thermal impedance was conducted under operating temperature variations (with virtual junction temperature ranging from 60.5 °C to 199.6 °C).
Abstract: This article characterizes the thermal behavior of a commercialized silicon carbide (SiC) power MOSFET module with special concerns on high-temperature operating conditions as well as particular focuses on SiC MOSFET dies. A temperature-dependent Cauer-type thermal model of the SiC MOSFET is proposed and extracted based on offline finite-element simulations. This Cauer model is able to reveal the temperature-dependent thermal property of each packaging layer, and it is suitable for the high-temperature thermal-profile prediction with sufficient computational efficiency. Due to the temperature-dependent thermal properties of the SiC die and ceramic material, the junction-heatsink thermal resistance can be increased by more than 10% under high-temperature conditions (up to 200 °C), which can considerably worsen thermal estimations of the SiC die and its packaging materials. Furthermore, the experimental measurement of transient thermal impedance was conducted under operating temperature variations (with virtual junction temperature ranging from 60.5 °C to 199.6 °C), and the effectiveness of the proposed temperature-dependent Cauer model was fully validated.
TL;DR: In this article, the avalanche capability of SiC planar/trench MOSFETs is systematically evaluated and analyzed over the temperature range of 90 to 340 K. The authors further explored the essential mechanisms and temperature dependence of avalanche failure under cryogenic conditions by combining many analysis methods such as TCAD simulations, unclamped inductive switching characterizations, and the transient junction temperature prediction.
Abstract: The avalanche ruggedness of power devices becomes a crucial issue to ensure the safe operation of the power conversion systems, particularly under the extreme temperature conditions. In this article, the avalanche capability of SiC planar/trench MOSFETs is systematically evaluated and analyzed over the temperature range of 90 to 340 K. Importantly, the essential mechanisms and temperature dependence of avalanche failure under cryogenic conditions are further explored by combining many analysis methods such as TCAD simulations, the unclamped inductive switching characterizations, and the transient junction temperature prediction. The highest avalanche energy density of 171.24 mJ/mm2 at 90K indicates the great application potential of SiC planner mosfet in cryogenic electronics. Moreover, the safe avalanche operation boundary (AOB) model is established over the cryogenic temperature range. The relevant analysis method and AOB model can be used to accurately evaluate and quantitatively predict the avalanche capability of SiC planar/trench mosfet s for the cryogenic converter design.
TL;DR: In this paper, two novel methods, the simulated Δ Zth and the Cauer thermal model, are proposed for the correction of the maximum junction temperature offset, and the principle and accuracy of these two methods are discussed in detail.
Abstract: The lifetime evaluation is strongly influenced by the measurement accuracy of the junction temperature with the V ce(T) method during power cycling test (PCT). However, the measurement delay time t md, the time between which the load current is switched off and the test pulse is applied, induces a maximum junction-temperature offset Δ Tjm . The JEDEC [1] suggested square root t method is found only to be suitable for devices with surface-close heat generation and will induce errors for other devices such as IGBTs. In this article, two novel methods, the simulated Δ Zth and the Cauer thermal model, are proposed. The principle and accuracy of these two methods are discussed in detail. Furthermore, the measured Zth curve, or the Foster thermal model method, is proven not suitable for the correction of the maximum junction-temperature offset, as it will induce the same error as the square root t method.
TL;DR: In this article, the relationship between circuit parameters and junction temperature of SiC MOSFETs is analyzed, and a junction temperature fluctuation tracking suppression strategy for SiC mOSFets is proposed, which consists of a coarse and a fine adjustment stage.
Abstract: In order to improve system reliability and reduce device thermal fatigue failure in multiload wireless power transfer (WPT) systems for electric vehicles, the implementation of the junction temperature fluctuation suppression strategy for SiC MOSFETs is necessary However, current methods are relatively lacking, and active thermal management has not been used in WPT systems In this article, the relationship between circuit parameters and junction temperature of SiC MOSFET is analyzed In particular, a junction temperature fluctuation tracking suppression strategy for SiC MOSFETs is proposed, which consists of a coarse and a fine adjustment stage As for the former, a shunt capacitor bank switching method is implemented In order to compensate for the coarse adjustment defects in the small adjustment range and poor effect, in fine adjustment stage, a changing driving voltage method is used Finally, a 5-kW multiload WPT system is built for verification Experimental results show that the proposed strategy has obvious effect on the suppression of junction temperature fluctuation and keeps temperature near the target temperature Benefiting from this, the maximum 139 °C junction temperature fluctuation is completely eliminated when the power fluctuations are within 361% of the rated power, and the heat load of each SiC MOSFET can be independently adjusted
TL;DR: In this article, the authors proposed an improved TDIM with the junction temperature compensation to improve the accuracy of 600-V discrete IGBT devices, and the experimental results showed that the improved TIM improved the accuracy by about 9.5% for 600-v IGBT.
Abstract: The transient dual interface method (TDIM), proposed by the JEDEC 51-14 standard [1] , determines the junction-to-case thermal resistance of power electronics with the separate point of two transient thermal impedance curves under different contact conditions. However, the influence of the junction temperature is not considered and this underestimates the actual value with earlier separation point. This phenomenon is presented first with experimental results at different junction temperatures. Electro-thermal finite element simulations and simulation with semiconductor physical behavior in the devices simulations are performed to explain the root reason. After that, the improved TDIM with the junction temperature compensation is proposed to improve the accuracy. The experimental results show that the improved TDIM improves the accuracy of about 9.5% for 600-V discrete IGBT devices.
TL;DR: In this paper, the impact of bias temperature instability (BTI) on the accurate junction temperature measurement using temperature sensitive electrical parameters (TSEPs) in SiC MOSFETs is discussed.
Abstract: Junction temperature sensing is an integral part of both online and offline condition monitoring where direct access to the bare die surface is not available. Given a defined power input, the junction temperature enables the estimation of the junction-to-case thermal resistance, which is a key indicator of packaging failure mechanisms like solder voiding and cracks. The use of temperature sensitive electrical parameters (TSEPs) has widely been proposed as a means of junction temperature sensing; however, there are certain challenges regarding their use in SiC MOSFETs. Bias temperature instability (BTI) from charge trapping in the gate dielectric causes threshold voltage drift, which in SiC affects some of the key TSEPs including on -state resistance, body diode forward voltage as well as the current commutation rate. This article reviews the impact of BTI on the accurate junction temperature measurement using TSEPs in SiC MOSFETs.
TL;DR: In this paper, the authors proposed a junction temperature estimation method for the IGBT module to adapt to various operating conditions and improve the computing efficiency by using the superposition theorem and odd/even mode analysis.
Abstract: This letter proposes a novel junction temperature estimation method for the IGBT module to adapt to various operating conditions and improve the computing efficiency. By using the superposition theorem and odd/even mode analysis, the input power loss is decomposed into the even and odd mode loss. Further, the thermal model considering the thermal coupling between the upper and lower arms is equivalently decomposed into the even and odd mode thermal model according to the structure symmetry. The odd mode power loss is the cause of the thermal coupling between the upper and lower arms, and the odd mode junction temperature variation is used as an indicator to measure the thermal coupling. Based on the frequency domain analysis, the dividing line for operating condition with weak thermal coupling and strong thermal coupling can be obtained. Finally, experimental results verify the validity of the theoretical analysis and the accuracy of the proposed thermal estimation method.
TL;DR: In this paper, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers, which facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN devices.
Abstract: Designing and optimizing high switching frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistances, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) switches was plagued by detrimental dynamic on-state resistance effects. This complex phenomenon for GaN devices is characterized by deviations in on-state resistance from dc operating characteristics based on design choices such as the magnitude and duration of both voltage and current stress, switching mode, and junction temperature. While device manufacturers have made improvements compared to early generation devices, experimental evidence from a survey of commercial GaN transistors highlight measurable change in on-state resistance still exists due to variations in voltage stress during hard-switching operation. After sharing insights for obtaining low noise measurements, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers. Quantifying the performance of GaN devices with standardized metrics facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN device development.
TL;DR: In this article, a transient 3D thermal modeling method for insulated gate bipolar transistor (IGBT) modules is proposed to obtain accurate temperature distribution considering uneven power losses and cooling conditions.
Abstract: Junction temperature is a key parameter for the safe operation of power semiconductor devices in power electronic systems. However, it is difficult to forecast the accurate thermal stress of the device in field use. Consequently, engineers tend to use higher rated devices to maintain excessive margin, resulting in a higher cost. In this article, a transient 3-D thermal modeling method for insulated gate bipolar transistor (IGBT) modules is proposed to obtain accurate temperature distribution considering uneven power losses and cooling conditions. The analytical model of uneven switching energy losses among the parallel IGBT chips in modules is built according to the analysis of device simulation results. The effect of uneven cooling conditions on temperature distribution in IGBT modules is considered by thermal-fluid cosimulation. Furthermore, a hybrid simulation strategy is proposed to obtain the transient thermal behavior in three dimensions. Through appropriate interface design, the power loss model is connected with the finite element model to achieve field-circuit cosimulation with multiple time steps, which takes full consideration of the multiphysical coupling effects among power loss, temperature, and flow fields. Finally, the thermal stresses of IGBT modules under different operating conditions are forecast by the proposed method.
TL;DR: The paralleling suitability of SiC MOSFETs and SiC/Si cascode devices is quantitatively evaluated by the unbalanced current among paralleled chips under the conditions with asymmetric layout and uneven junction temperature.
Abstract: SiC metal-oxide semiconductor field-effect transistors (MOSFETs) and SiC/Si cascode devices are two popular normally-off SiC power devices. In terms of the rated voltage and current of a single chip, there are always some SiC/Si cascode counterparts for the SiC MOSFETs.Thus, the two devices can substitute for each other in many fields. However, it is not clear which of the two SiC power devices is more suitable for parallel operation to deal with high current. This paper comparatively investigates the paralleling suitability of SiC MOSFETs and SiC/Si cascode devices by theoretical analysis and experimental verifications for the first time. The paralleling suitability of the two devices is quantitatively evaluated bythe unbalanced current among paralleled chips under the conditions with asymmetric layout and uneven junction temperature. Both static and dynamic imbalanced current are taken into consideration. Based on the theoretical and experimental results, some design guidelines are proposed to promote current sharing.
TL;DR: In this paper, a sequential V ce(T ) method with separated gate controller is proposed to measure the junction temperature distribution within press-pack insulated gate bipolar transistors (PP IGBTs), which is not possible for traditional temperature measurement methods due to the enclosed structure and external clamping force of the pressure-type package.
Abstract: In this article, a sequential V ce( T ) method with separated gate controller is proposed to measure the junction temperature distribution within press-pack insulated gate bipolar transistors (PP IGBTs), which is not possible for traditional temperature measurement methods due to the enclosed structure and external clamping force of the pressure-type package. This proposed method is integrated into a standard dc power cycling test and the steady-state junction temperature distribution is obtained to validate its applicability and effectiveness. The measured junction temperature exhibited a bathtub type distribution within PP IGBTs. The root cause is the deformation of the copper plate, which was also discussed by the finite-element simulation in previous literature. Furthermore, the influence of static characteristic dispersion is excluded by the chip transposition and the thermomechanical coupling effect is confirmed to be the dominant factor of this junction temperature distribution. Finally, the influence of heating current and heating time on junction temperature distribution is also investigated by the proposed method.
TL;DR: In this article, an electrothermo-mechanical multiphysics field-circuit coupling model of PP IGBT, coupled with the electrical, thermal, and mechanical fields, is proposed to predict collector current, clamping force, and junction temperature.
Abstract: Press pack insulated gate bipolar transistor (PP IGBT) is suitable for the hybrid high voltage direct current (HVdc) breaker to clear the fault current of the flexible HVdc transmission system with its advantages of double-side cooling, short-circuit failure mode, and easy to connect in series. However, it should have the ability to transmit the fault current, which is up to five or six times of its rated current, within several milliseconds depending on the distances between two stations without external cooling system. The junction temperature of PP IGBT will increase sharply and it is not possible to be measured during that situation. Therefore, the accurate prediction of junction temperature is extremely important for the packaging design of PP IGBT according to its working condition. In this article, an electro-thermo-mechanical multiphysics field-circuit coupling model of PP IGBT, which is coupled with the electrical, thermal, and mechanical fields, is proposed to predict the collector current, clamping force, and junction temperature. The 3-D mechanical model is decoupled with the 1-D electro-thermal Cauer network model to simplify this multiphysics model without reducing its accuracy. Both the normal and worst working conditions are analyzed through this multiphysics field-circuit model.