Topic
Junction temperature
About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.
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13 Mar 1989
TL;DR: In this article, the authors characterized the avalanche-current capability of power MOSFETs under unclamped inductive switching (UIS) conditions and showed that the maximum avalanche current decreases linearly with initial junction temperature, indicating a thermally initiated failure mechanism.
Abstract: The avalanche-current capability of a new class of power MOSFETs called MegaFETs is characterized under UIS (unclamped inductive switching) conditions. These devices are shown to be limited in avalanche current only when the junction temperature exceeds the intrinsic temperature of 425 degrees C. Second breakdown is shown to occur independent of the parasitic bipolar transistor. The devices tested exhibit a cubic relationship between the maximum avalanche current and inductance, which represents a nonconstant energy capability. This maximum current decreases linearly with initial junction temperature, indicating a thermally initiated failure mechanism. The maximum junction temperature at failure was found to be 400-450 degrees C. The power-supply voltage reduces the maximum avalanche current by increasing the time in avalanche. The current capability is also proportional to total die area when the avalanche time is constant. The avalanche-current capability of a planar diode was found to verify that parasitic bipolar turn-on is not necessary to cause second breakdown. Second breakdown due to the thermal generation of carriers represents the limiting boundary of power-MOSFET avalanche-current capability. >
31 citations
18 Jun 2006
TL;DR: In this article, a novel electro-thermal coupling simulation technique mainly focused on the dynamic analysis of the HV inverter during WOT (Wide Open Throttle) operation is described.
Abstract: This paper describes a novel electro-thermal coupling simulation technique mainly focused on the dynamic analysis of the HV inverter during WOT (Wide Open Throttle) operation. This technique can predict the junction temperature of power devices installed within the power module accurately. This simulation technique is composed of an inverter circuit model including power semiconductor device models, a novel compact thermal model suitable for automotive power modules and motor model. Various information and conditions such as motor current, motor rotation speed, switching frequency and variable DC-link voltage are applied to the simulation for carrying out the WOT operation. The comparison between the simulated and measured results indicates that this method offers reasonable accuracy for the IGBT temperature estimation where the worst case error in the IGBT temperature is less than 10 deg-C. It takes 210 min to complete the WOT simulation with duration of 4 seconds.
31 citations
TL;DR: In this article, the avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT.
Abstract: In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) test are investigated and compared with Si IGBT. The experimental results show that SiC MOSFET can handle ∼20% higher avalanche energy at the same current density, and ∼50% higher current density at the same amount of energy. As SiC device has 5× smaller chip size, the advantage will disappear when comparison is performed with avalanche current. To improve the avalanche current capability of SiC MOSFET, failure mechanisms are analyzed. At first, the junction temperature is calculated with V-T model and thermal model, from which a linear dependence of temperature on avalanche current is revealed. Then, the probability of parasitic BJT turn-on is modeled analytically with the base-to-emitter resistance/voltage, which is found to be highly dependent on the p+ ohmic contact resistance (ρc) and base doping concentration (NB) designs of the device. Based on the modeling results, at the peak junction temperature 650 K in UIS test, the BJT turn-on can already be triggered for SiC MOSFET. The failure trigger temperature can be raised with a higher NB and lower ρc design, thus the avalanche current capability can be increased accordingly. On the other hand, with a much deeper p+ body structure design, the Si IGBT can prevent the BJT latch-up failure. Based on the failure analysis, a trench source structure of SiC MOSFET is proposed to further improve the avalanche capability for smaller chip size design.
31 citations
TL;DR: In this article, a temperature conditioning unit that allows the adjustment of the junction temperature between −40°C and 200°C using thermoelectric coolers (TECs) is presented.
Abstract: Accurate characterization of power semiconductors over wide operating ranges is a necessity to accomplish better electrical and thermal designs of power converters. Especially, switching losses of power devices are rarely given sufficiently detailed in their datasheets, since they also depend strongly on the driving circuitry and design of the power converter itself. A means to extract the switching losses are double pulse measurements where the desired operating points can be freely chosen. This paper introduces a temperature conditioning unit that allows the adjustment of the junction temperature between −40 °C and 200 °C using thermoelectric coolers (TECs). The unit is for an automated double pulse test bench with dc-link voltages of up to 1 kV and switching currents of up to 1 kA. Up to 1 kW of electrical power is required to power the TECs. The design of the power converter is shown as well as the control scheme. An algorithm, which automatically extracts the switching losses of the measured double pulse waveforms is presented. An exemplary characterization of an Infineon EconoDual power module is conducted and the results are presented.
31 citations
TL;DR: The reliability of high-performance AlInAs/GaInAs heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy (MBE) is discussed in this article.
Abstract: The reliability of high-performance AlInAs/GaInAs heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy (MBE) is discussed. Devices with a base Be doping level of 5*10/sup 19/ cm/sup -3/ and a base thickness of approximately 50 nm displayed no sign of Be diffusion under applied bias. Excellent stability in DC current gain, device turn-on voltage, and base-emitter junction characteristics was observed. Accelerated life-test experiments were performed under an applied constant collector current density of 7*10/sup 4/ A/cm/sup 2/ at ambient temperatures of 193, 208, and 328 degrees C. Junction temperature and device thermal resistance were determined experimentally. Degradation of the base-collector junction was used as failure criterion to project a mean time to failure in excess of 10/sup 7/ h at 125 degrees C junction temperature with an associated activation energy of 1.92 eV. >
31 citations