Topic
Junction temperature
About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.
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TL;DR: In this paper, the idealized concept of thermal resistance as applied to power transistors is discussed and various electrical methods for measuring the junction temperature (thermal resistance) of transistors with the emphasis placed on the emitter-only switching measurement technique, which is the preferred standard method of measurement.
Abstract: The idealized concept of thermal resistance as applied to power transistors is discussed. This concept must be used with care because two of the basic assumptions made in applying the concept to these devices are not valid. Contrary to these assumptions, it is shown that 1) the junction temperature of a power transistor is never spatially uniform, and 2) no unique value of thermal resistance can be defined for all operating conditions. Also, various electrical methods for measuring the junction temperature (thermal resistance) of power transistors are discussed with the emphasis placed on the emitter-only switching measurement technique, which is the preferred standard method of measurement. In addition, the generation and meaning of forward-biased safe-operating-area (SOA) limits are discussed, and it is shown that because of the presence of current crowding and the associated hotspots, the specified SOA limits often permit devices to be operated at dangerously high junction temperatures. Electrical measurement methods capable of determining the peak junction temperature as well as determining the onset of current crowding are described, and it is shown how these methods might be used for the generation of improved SOA limits.
109 citations
TL;DR: In this article, a custom designed accelerated aging platform that can expose multiple discrete power MOSFETs to thermal stress simultaneously is introduced, based on the collected experimental data, the variation of the on-state resistance is identified as the failure precursor, and an exponential degradation model that fits successfully with the experimental data are developed.
Abstract: The research on noninvasive incipient fault diagnosis of power converters is very critical to avoid strenuous periodic check-ups and costly interruptions. Thermal cycling is one of the main techniques to accelerate the package-related failure progress. In this paper, first, a custom designed accelerated aging platform that can expose multiple discrete power MOSFETs to thermal stress simultaneously is introduced. Based on the collected experimental data, the variation of the on -state resistance is identified as the failure precursor, and an exponential degradation model that fits successfully with the experimental data are developed. The remaining useful lifetime (RUL) of degraded power MOSFETs is estimated through classical least-squares algorithm run on experimental data filtered by Kalman Filter which deals with the measurement noise and model uncertainties. The essential advantage of the proposed method is that it does not require junction temperature information. The RUL estimation with limited field data is demonstrated on a number of experimental results.
108 citations
TL;DR: In this article, a comparison of silicon and SiC device technologies for the use in hybrid electric vehicle traction inverters is presented and a scalable loss and scalable thermal modeling approach is used to find the optimum chip area for each Si or SiC traction inverter.
Abstract: Silicon carbide (SiC) based power semiconductors are expected to contribute to an increase in inverter efficiency, switching frequencies, maximum permissible junction temperature, and system power density. This paper presents a comparison of silicon (Si) and SiC device technologies for the use in hybrid electric vehicle traction inverters. SiC-JFETs and SiC-MOSFETs are characterized and a scalable loss and scalable thermal modeling approach is used to find the optimum chip area for each Si or SiC traction inverter. This procedure also provides a proper technical comparison of the semiconductor technologies. The progressed simulations using standardized drive cycles and thermal-electrical coupled semiconductor models permit an inverter performance evaluation close to real load situations, leading to an improved estimation of the benefit which can be expected from systems utilizing SiC technology. This paper concludes that the SiC devices can lead to a reduction in chip area and semiconductor losses by more than 50% at the same time in hard switching applications with partial load dominated mission profiles.
108 citations
TL;DR: In this paper, the performance degradation of SiC MOSFETs during high-temperature operation is observed and discussed, and the degradation happens during both the high temperature storage and high temperature operation process.
Abstract: SiC MOSFET devices have great potentials in future high temperature power electronics applications due to their possible higher thermal runaway temperature compared with other SiC power semiconductor devices. In this paper, the high temperature stability of SiC MOSFETs is investigated by experiments and Saber simulations. The maximum steady-state junction temperature of the SiC MOSFET is measured to exceed 250 °C and saber simulations based on experimental model estimate that the thermal runaway temperatures are close to 300 °C. In addition, performance degradation of SiC MOSFETs during high-temperature operation is observed and discussed. Experimental results show that the degradation happens during both the high temperature storage (maximum 5% RON increment) and high temperature operation process (maximum 15% RON increment). The degradations are found to recover to a close-to-initial level after 1 h recovery time at the room temperature.
106 citations
Patent•
12 Dec 1996
TL;DR: In this paper, a bias circuit for a power amplifier is proposed to reduce key-up time by reducing the distortion caused by the output transistor's junction temperature change during the transmission.
Abstract: A biasing circuit for a power amplifier, for use in a transmitter, that substantially reduces distortion during key-up and thereby reduces key-up time. The power amplifier includes an output transistor and a bias circuit. The bias circuit is applied to all the class AB stages of the power amplifier. The bias circuit provides to the output transistor a first bias level during the preheat period and a second bias level during the transmit period. This first bias level is predetermined to cause the output transistor to reach the steady-state junction temperature achieved by the output transistor during the transmit period (i.e., when transmitting output signals biased with the second bias level). The preheat period ends when this steady-state temperature is reached. Thus, the power amplifier can then transition to a transmit period having already reached the steady-state junction temperature. Because the output transistor is already heated to the steady-state junction temperature, "thermal" distortion (i.e., the distortion incurred when the output transistor's junction temperature changes while transmitting) is avoided and the key-up time is reduced.
106 citations