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Junction temperature

About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.


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Proceedings ArticleDOI
12 Mar 2002
TL;DR: In this paper, the influence of board conduction on the predictive accuracy of Compact Thermal Models of BGA and CPGA package styles was performed, and the impact of board conductivity on CTM accuracy was investigated.
Abstract: The application and use of Compact Thermal Models of single chip electronic packages in a board level environment has seen limited study. In particular the influence of board thermal characteristics on the predictive accuracy of CTMs generated independently of the board is not well understood. A systematic study of the influence of board conduction on the predictive accuracy of Compact Thermal Models of BGA and CPGA package styles was performed. For the CPGA special attention was given to the socket model. The compact model parameters were extracted using a standard optimization procedure to best reproduce the junction temperature and heat flows computed for the detailed models exposed to a reduced set of heat transfer coefficients on the prime lumped areas. Various resistance network topologies were assessed for each package style. Detailed (FE) isotropic board models with conductivities spanning three orders of magnitude were created to test the influence of board conductivity on CTM accuracy. The board models included fully detailed isotropic models of the 1S0P and 1S2P JEDEC standard thermal test boards.

20 citations

Journal ArticleDOI
Wei Lai1, Xianming Liu1, Weimin Chen1, Xiaohua Lei1, Xueying Cao1 
TL;DR: In this article, a dynamic compact thermal model is constructed for an independent HP LED without being attached on a cold plate, and the time-constant spectrum method based on the thermal model was applied to characterize the transient thermal behavior of the DAA layer and other layers along the heat flow path.
Abstract: The performance and reliability of the high-power light-emitting diodes (HP LEDs) are closely related to the quality of the die attach adhesive (DAA) layer, because voids or delaminations in the layer may cause higher junction temperature, and even result in the break of the chip. In this paper, a dynamic compact thermal model is constructed for an independent HP LED without being attached on a cold plate. The time-constant spectrum method based on the thermal model is applied to characterize the transient thermal behavior of the DAA layer and other layers along the heat flow path. Thermal transient experiments are carried on HP LED samples with different DAA dosages. The theoretical and experimental results demonstrate that the time-constant spectrum for LEDs tested without cold plate can reflect the thermal characteristics of the DAA layer as well as that with cold plate. Differences in the HP LED samples with different DAA layers can be obviously distinguished in the time-constant spectrums as well. Compared with the traditional testing method with cold plate, direct test in air for HP LEDs has the advantages of easy operation, time saving, and no pollution to samples.

20 citations

Journal ArticleDOI
TL;DR: In this paper, the thermal performance limits of a flip-chip package with a direct-chip attach (DCA) interconnect were investigated under both free air and forced air conditions.
Abstract: This study projects the thermal performance limits of a flip chip package. A plastic, pin grid array (PGA) package with direct chip attach (DCA) interconnect was chosen for the demonstration purpose. The same methodology as developed here can be applied to other flip chip packages, The design rules chosen are the allowable power dissipation for constraints of junction temperature (/spl les/105/spl deg/C) and board temperature (/spl les/90/spl deg/C) under either free air or forced air (1.27 m/s) condition. An experimentally validated computational fluid dynamics (CFD) model was used to predict the thermal performance limits of the flip chip package. Simulations were run by increasing the power to the package under consideration until either the junction temperature or the board temperature reached its limit. Based on these constraints, the allowable power dissipation in the package was determined to be between 1.7 and 6.7 W in free air and between 2.1 and 13.7 W in 1.27 m/s of air. The validated CFD models offer enormous potential to quickly assess thermal limits of many future flip chip packages and their variations.

20 citations

Journal ArticleDOI
TL;DR: In this paper, a thermal characterization method of power semiconductor devices based on an H-bridge testing circuit, as well as its corresponding control and measurements, is proposed, where a current controller is used to cut off the heating current rapidly and thus contribute to more accurate estimation of thermal impedance.
Abstract: This letter proposes a thermal characterization method of power semiconductor devices based on an H-bridge testing circuit, as well as its corresponding control and measurements. In the proposed method, the power semiconductor devices under test (DUTs) operate under the switching mode, which is closer to the practical use. Due to the presence of switching loss, similar ranges of junction temperature can be achieved with much lower heating current than the one in the conventional testing method. Besides, a current controller is used to cut off the heating current rapidly, so that the proposed method can approximate an ideal step power loss and thus contribute to more accurate estimation of thermal impedance. In addition, the proposed testing method enables multiple DUTs and repeated measurements, in order to take parameter distribution and uncertainty into account. The feasibility, control, and some electrical behaviors of the proposed method are verified through experimental tests.

20 citations

Proceedings ArticleDOI
09 Feb 2006
TL;DR: In this paper, the authors used temperature and bias-dependent power degradation measurements to determine possible degradation mechanisms and showed that the output power decays with two characteristic time constants indicating two degradation mechanisms.
Abstract: Deep UV LEDs emitting at on 280 nm with powers as high as 1 mW at 20 mA have been reported recently. These devices have mesa size of 100 μm x 100 μm to avoid current crowding due to the high Al-composition of the AlxGa 1-x N buffer layers. Small mesa size results in pump current density of 200 A/cm 2 for a device current of 20 mA. Small area of p-contact also leads to higher operating voltage and higher thermal impedance for the flip-chip packaged device. These factors limit the device lifetime for 50 % power reduction to only a few hundred hours. From temperature and bias dependent power degradation measurements we found the output power to decay with two characteristic time constants indicating two degradation mechanisms. The faster time constant is bias dependent and temperature independent. The slower time constant varies exponentially with junction temperature having the activation energy of 0.27 eV at 200 A/cm 2 pump current density. For the devices with high thermal impedance this degradation mechanism controls the long term power degradation. To increase the device area for better reliability we used the interconnected micro-pixel device design with 10x10 array of 22 μm in diameter pixels. This design allowed for the four-fold increase of the junction area and thereby led to improved reliability performance with the operation life-time for 50 % power reduction of about 1000 hours. In this paper we will present the details of the reliability measurements and use the experimental results to determine possible degradation mechanisms.

20 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023118
2022277
2021233
2020287
2019334
2018303