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Junction temperature

About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.


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Journal ArticleDOI
Jose Ortiz Gonzalez1, Olayiwola Alatise1, Ji Hu1, Li Ran1, Philip Mawby1 
TL;DR: In this paper, the authors examined dynamic temperature-sensitive electrical parameters (TSEPs) for SiC MOSFETs and showed that the switching rate of the output current coupled with the gate current plateau (I GP) during turn-ON could be an effective TSEP under specific operating conditions.
Abstract: This paper examines dynamic temperature-sensitive electrical parameters (TSEPs) for SiC MOSFETs. It is shown that the switching rate of the output current ( dI DS /dt ) coupled with the gate current plateau (I GP) during turn-ON could be an effective TSEP under specific operating conditions. Both parameters increase with the junction temperature of the device as a result of the negative temperature coefficient of the threshold voltage. The temperature dependency of dI DS /dt has been shown to increase with the device current rating (due to larger input capacitance) and external gate resistance ( $R_{G}^{\rm EXT}$ ). However, as dI DS /dt is increased by using a small $R_{G}^{\rm EXT}$ , parasitic inductance suppresses the temperature sensitivity of the drain and gate current transients by reducing the “effective gate voltage” on the device. Since the temperature sensitivity of dI DS /dt is at the highest with maximum $R_{G}^{\rm EXT}$ , there is a penalty from higher switching losses when this method is used in real time for junction temperature sensing. This paper investigates and models the temperature dependency of the gate and drain current transients as potential TSEPs for SiC power MOSFETs.

91 citations

Journal ArticleDOI
TL;DR: In this article, a measurement system for thermal impedance is developed to evaluate three die-attach materials, and the experimental results show that, after 500 cycles, the thermal impedance of SAC305 samples and SN100C samples is increased by 12.9% and 13.3%, respectively, which is much higher than that of the sample using the sintered nano-silver for the die attach (3.1%).
Abstract: Since a die-attach layer has a significant impact on the thermal performance of a power module, its quality can be characterized using thermal performance. In this paper, a measurement system for thermal impedance is developed to evaluate three die-attach materials. Thanks to its high temperature sensitivity (10 mV/°C), the gate-emitter voltage of an insulated gate bipolar transistor (IGBT) is used as the temperature-sensitive parameter. The power dissipation in the IGBT remains constant by a feedback loop, regardless of the junction temperature. Experimental results show that the sample using sintered nano-silver for the die-attach has 12.1% lower thermal impedance than the samples using SAC305 and SN100C solders. To check the degradation of the die-attachment, six samples using three die-attach materials were thermally cycled from -40 to 125°C. The experimental results show that, after 500 cycles, the thermal impedance of SAC305 samples and SN100C samples is increased by 12.9% and 13.3%, respectively, which are much higher than that of the sample using the sintered nano-silver for the die-attach (3.1%).

90 citations

Journal ArticleDOI
TL;DR: In this paper, a phase-leg power module is packaged by a novel planar packaging technique for high-temperature (250°C) operation, where the nanosilver paste is chosen as the die-attach material as well as playing the key functions of electrically connecting the devices' pads.
Abstract: This paper presents the design, development, and testing of a phase-leg power module packaged by a novel planar packaging technique for high-temperature (250°C) operation. The nanosilver paste is chosen as the die-attach material as well as playing the key functions of electrically connecting the devices' pads. The electrical characteristics of the SiC-based power semiconductors, SiC JFETs, and SiC Schottky diodes have been measured and compared before and after packaging. No significant changes (<;5%) are found in the characteristics of all the devices. Prototype module is fabricated and operated up to 400 V, 1.4 kW at junction temperature of 250°C in the continuous power test. Thermomechanical robustness has also been investigated by passive thermal cycling of the module from -55°C to 250°C. Electrical and mechanical performances of the packaged module are characterized and considered to be reliable for at least 200 cycles.

90 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed a transient thermal model for IGBT junction temperature simulations during short circuits or overloads using finite element method (FEM) thermal simulations with temperature-dependent physical parameters.
Abstract: A basic challenge in the insulated gate bipolar transistor (IGBT) transient simulation study is to obtain the realistic junction temperature, which demands not only accurate electrical simulations but also precise thermal impedance. This paper proposed a transient thermal model for IGBT junction temperature simulations during short circuits or overloads. The updated Cauer thermal model with varying thermal parameters is obtained by means of finite-element method (FEM) thermal simulations with temperature-dependent physical parameters. The proposed method is applied to a case study of a 1700 V/1000 A IGBT module. Furthermore, a testing setup is built up to validate the simulation results, which is composed of a IGBT baseplate temperature control unit, an infrared camera with a maximum of 3 kHz sampling frequency, and a black-painted open IGBT module.

90 citations

Proceedings ArticleDOI
07 Feb 1995
TL;DR: In this article, the average chip temperature due to multiple sources within the module was considered as the reference temperature for evaluating the junction temperature rise of a particular chip. And the concept of superposition of temperatures was found to capture the effect of the background heating of the chip due to its neighbors as well as the individual power dissipation from the chip in question.
Abstract: Multichip modules provide shorter interconnection lengths between the chips, higher speeds and lower costs. This higher system performance is the driving force for advances in MCM packaging technology. A potential limitation is the ability to remove heat from these packages. With higher chip densities, the thermal management of multichip modules poses a real challenge to the package manufacturer. There is a need to define the junction-to-ambient and junction-to-case thermal resistances for multichip modules in a more rigorous manner while reducing the number of thermal tests needed to evaluate an MCM and provide information to predict junction temperatures under arbitrary powering up of the individual dice. For high reliability, it is critical that maximum specified operating junction temperatures are not exceeded. Experiments were performed for nonuniform powering up of an MCM mounted on a vertical board in natural and forced convection. The package tested was a 208-lead Amkor PMCM. The average chip temperature due to multiple sources within the module was considered as the reference temperature for evaluating the junction temperature rise of the particular chip. The concept of superposition of temperatures was found to capture the effect of the background heating of the chip due to its neighbors as well as the individual power dissipation from the chip in question. This approach offers a more refined methodology for evaluation of nonuniformly powered multichip modules compared to previous methods.

90 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023118
2022277
2021233
2020287
2019334
2018303