Topic
Junction temperature
About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.
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01 Jan 2011
TL;DR: In this paper, the authors used finite element thermal simulations of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) to evaluate the impact of device design parameters on the junction temperature, in particular the effects of substrate thickness, substrate thermal conductivity, GaN thickness, and GaN-to-substrate thermal boundary resistance on device temperature rise.
Abstract: The present work uses finite element thermal simulations of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) to evaluate the impact of device design parameters on the junction temperature. In particular the effects of substrate thickness, substrate thermal conductivity, GaN thickness, and GaN-to-substrate thermal boundary resistance (TBR) on device temperature rise are quantified. In all cases examined, the TBR was a dominant factor in overall device temperature rise. It is shown that a TBR increase can offset any benefits offered through a more conductive substrate and that there exists a substrate thickness independent of TBR which results in a minimum junction temperature. Additionally, the decrease of GaN thickness only provides a thermal benefit at small TBRs. For TBRs on the order of 10 -4 cm 2 K/W or greater, decreasing the GaN thickness can actually increase the temperature as the heat from the highly localized source is not sufficiently spread out before crossing the GaN-substrate boundary. The tradeoff between GaN heat spreading, substrate heat spreading, and temperature rise across the TBR results in a GaN thickness with minimum total temperature rise. For the TBR values of
17 citations
TL;DR: In this paper, high output power from AlInGaN multiple quantum well (MQW) ultraviolet light-emitting diodes was reported, where the high Al containing cladding layer, electron blocking layer and p-contact layer were chosen for transparency at 365nm to reduce the internal absorption, reduce electron overflow and enhance output power.
17 citations
Patent•
26 Sep 2000
TL;DR: In this paper, a ripple temperature detector is used to measure the ripple temperature from the base plate temperature detection value in the unit measuring period of operation/stop by a temperature range, a counter counts the number of the times of generation for each ripple temperature every unit measurement period, and a life time calculation part 16 estimates the life time L(1/CD) from an accumulated damage rate.
Abstract: PROBLEM TO BE SOLVED: To solve such a problem that it takes labor and time to estimate the life time of a semiconductor power converter and life time prediction based on the number of the time of switching of an element, but life time prediction becomes rough when based on the junction temperature. SOLUTION: A temperature detector 10 measures the base plate temperature of IGBT of an inverter 2, a ripple temperature detector 13 measures the ripple temperature from the base plate temperature detection value in the unit measuring period of operation/stop by a temperature range, a counter 14 counts the number of the times of generation for each ripple temperature every unit measuring period, a power damage rate calculation part 15 finds an accumulated damage rate CD from the number of the times of the life time by temperature range for the ripple temperature and the number of the times of practical generation, and a life time calculation part 16 estimates the life time L(=1/CD) from an accumulated damage rate.
17 citations
03 Nov 2003
TL;DR: This paper investigates the thermal management of high performance chips in the burn-in environment and finds that if the temperature is not controlled, it may lead to the thermal runaway.
Abstract: In deep sub-micron CMOS technologies, increased standby current in high performance processors results in increased junction temperature. This elevated temperature has a positive feedback on the standby current. If the temperature is not controlled, it may lead to thermal runaway. In this paper we investigate the thermal management of high performance chips in the burn-in environment.
17 citations
22 Apr 2014
TL;DR: This work has used Verilog as HDL and Xilinx ISE 14.6 as simulator to design the voltage based efficient fire sensor and has used four different kinds of Stub Series Terminated Logic (SSTL)IO standards.
Abstract: In this paper an approach is made to design the voltage based efficient fire sensor and for that reason we have used four different kinds of Stub Series Terminated Logic (SSTL)IO standards. Airflow and heat sink are main parameters while analyzing the thermal dissipation in the circuit. In this work we have taken two values for LFM i.e. 250, 500 and three profiles for heat sink are taken, these are low profile, medium profile and high profile. When the voltage sensor is operating at 1THz and LFM is 250 with low profile heat sink, junction temperature of SSTL135_DCI is reduced up to 5.12% 6.03% and 20.77% as compared to SSTL12, SSTL12_DCI and SSTL135_R respectively. Under same operating frequency and heat sink profile with LFM as 500, we are achieving 3.69%, 5.22% and 17.99% less junction power reduction in SSTL135_DCI with respect to SSTL12, SSTL12_DCI and S S TL135_Rrespectively. This design is implemented on Kintex-7 FPGA, XC7K70T device and −3 speed grades. In this work we have used Verilog as HDL and Xilinx ISE 14.6 as simulator.
17 citations