Junction temperature

About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.

Performance Evaluation of Waste Heat Recovery Systems Based on Semiconductor Thermoelectric Generators for Hypersonic Vehicles

Abstract: The types and the characteristics of the waste heat on hypersonic vehicles and the application feasibility of thermoelectric generators (TEGs) for hypersonic aircraft are discussed in this paper. Two thermoelectric generator schemes with an isothermal heat source and a variable temperature heat source were proposed, and the corresponding models were developed to predict the performance of the waste heat recovery systems on a hypersonic vehicle with different heat sources. The thermoelectric efficiency variation with electric current, the temperature distribution of fuel and junctions, and the distribution of the thermoelectric figure of merit (ZT value) are described by diagrams. Besides, some improvements for a better performance are analyzed. The results indicate that the maximum values of thermoelectric efficiency are 5% and 2.5% for the isothermal heat source and the variable temperature heat source, respectively, and the thermoelectric efficiency improves with the temperature of the hot junction. The performance of the TEGs with variable temperature heat source is worse than that of the other TEGs under the same highest hot junction temperature conditions, and the former has a better conversion efficiency than the latter when the average temperatures are identical.

Techniques and system for managing platform temperature

Abstract: In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.

Trends in Submicrometer InP-Based HBT Architecture Targeting Thermal Management

Abstract: More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.

Multidisciplinary Placement Optimization of Heat Generating Electronic Components on a Printed Circuit Board in an Enclosure

Abstract: A multidisciplinary placement optimization methodology for heat generating electronic components on a printed circuit board (PCB) subjected to forced convection in an enclosure is presented In this methodology, thermal, electrical, and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location are optimized simultaneously using the genetic algorithm A board-level thermal performance prediction methodology based on channel flow forced convection boundary conditions is developed The methodology consists of a combination of artificial neural networks (ANNs) and a superposition method that is able to predict PCB surface and component junction temperatures in a much shorter calculation time than the existing numerical methods Three ANNs are used for predicting temperature rise at the PCB surface caused by a single heat source at an arbitrary location on the board, while temperature rise due to multiple heat sources is calculated using a superposition method Compact thermal models are used for the electronic components thermal modeling Using this optimization methodology, large calculation time reduction is achieved without losing accuracy To demonstrate its capabilities, the present methodology is applied to a test case involving multiple heat generating component placement optimization on a PCB

Thermal Characterization of Silicon Carbide MOSFET Module Suitable for High-Temperature Computationally Efficient Thermal-Profile Prediction

Abstract: This article characterizes the thermal behavior of a commercialized silicon carbide (SiC) power MOSFET module with special concerns on high-temperature operating conditions as well as particular focuses on SiC MOSFET dies. A temperature-dependent Cauer-type thermal model of the SiC MOSFET is proposed and extracted based on offline finite-element simulations. This Cauer model is able to reveal the temperature-dependent thermal property of each packaging layer, and it is suitable for the high-temperature thermal-profile prediction with sufficient computational efficiency. Due to the temperature-dependent thermal properties of the SiC die and ceramic material, the junction-heatsink thermal resistance can be increased by more than 10% under high-temperature conditions (up to 200 °C), which can considerably worsen thermal estimations of the SiC die and its packaging materials. Furthermore, the experimental measurement of transient thermal impedance was conducted under operating temperature variations (with virtual junction temperature ranging from 60.5 °C to 199.6 °C), and the effectiveness of the proposed temperature-dependent Cauer model was fully validated.