Topic
Junction temperature
About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.
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17 Oct 2013
TL;DR: In this article, the Miller plateau width (in the Vge waveform) depend linearly on the junction temperature of the IGBT chips, and a measurement circuit was implemented at gate level to measure the involved time duration and its functionality was demonstrated for different types of IGBT modules.
Abstract: The paper presents a novel method for online estimation of the junction temperature (Tj) of semiconductor chips in IGBT modules, based on evaluating the gate-emitter voltage (Vge) during the IGBT switch off process. It is shown that the Miller plateau width (in the Vge waveform) depend linearly on the junction temperature of the IGBT chips. Hence, a method can be proposed for estimating the junction temperature even during converter operation - without the need of additional thermal sensors or complex Rth network models. A measurement circuit was implemented at gate level to measure the involved time duration and its functionality was demonstrated for different types of IGBT modules.
61 citations
11 Mar 2008
TL;DR: In this article, different power cycling tests, failure mechanisms and possible improvements are described. But the main challenge is the packaging technology. And this paper focuses on the power cycling test.
Abstract: Applications of power electronic devices in hybrid electric cars demand a higher allowed junction temperature of the power devices, if compact inverters close to the engine which use the combustion engine cooling circuit (with water temperatures up to T=115deg C) are required. Main challenge is the packaging technology. This paper reports on different power cycling tests, failure mechanisms and possible improvements.
61 citations
TL;DR: In this paper, the authors developed a simple non-destructive method to measure the solar cell junction temperature of PV module, where the PV module was put in the environmental chamber with precise temperature control to keep the solar PV module as well as the cell junction in thermal equilibrium with the chamber.
61 citations
04 Mar 2018
TL;DR: In this paper, a dual-interleaved, 9-level FCML inverter was demonstrated in the laboratory with a 1 kV input bus voltage and 9.7 kW output power, achieving a gravimetric power density of 17.3 kW/kg.
Abstract: Realizing the electrification of aircraft necessitates the development of inverters and rectifiers with ultra-high efficiency and specific power simultaneously. Unconventional topologies such as the flying capacitor multilevel (FCML) inverter hold great promise for achieving transformational reductions in inverter power loss and weight due to drastically smaller filters and compact hybrid energy transfer mechanism. After describing methods to overcome obstacles in ultra-efficient and lightweight converter design, this work presents an example of interleaved FCML inverter operation. The successful, balanced interleaved operation was demonstrated in the laboratory with a dual-interleaved, 9-level converter prototype at 1 kV input bus voltage and 9.7 kW output power. At 98.6% peak efficiency, this converter achieves a gravimetric power density of 17.3 kW/kg and a volumetric power density of 35.3 kW/L including the contributions of the heat sink. Interestingly, observations from loss modeling and hardware efficiency measurements revealed the large impact of second-order loss mechanisms, such as dynamic on-state resistance and junction temperature. Insights gained from this new understanding can be incorporated into future modeling for more thorough optimization of the converter design.
61 citations
Patent•
22 Mar 1978
TL;DR: In this article, a monolithic integrated complementary metal oxide semiconductor (CMOS) circuit senses internal junction temperature and converts it to a binary coded decimal output signal using a very stable amplifier.
Abstract: A monolithic integrated complementary metal oxide semiconductor (CMOS) circuit senses internal junction temperature and converts it to a binary coded decimal output signal. The circuit compares a temperature dependent junction voltage with a bandgap reference voltage controlled by a very stable amplifier. The comparison differential is then converted to a binary coded decimal output signal by an analog to digital converter. The circuit utilizes parasitic bipolar NPN transistor elements formed from a substrate of the chip in a conventional CMOS fabrication process. The principles of the present invention are also broadly applicable to other semiconductor technologies such as integrated injection logic (I 2 L).
61 citations