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Junction temperature

About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.


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Proceedings ArticleDOI
21 Jun 2010
TL;DR: In this paper, a measurement system for thermal impedance is developed to evaluate three die-attach materials, and three samples using three die attach materials were thermally cycled from -400C to 1250C, and the experimental results show that after 500 cycles, the thermal impedance of SAC305 samples and SN100C samples is increased by 12.8% and 15% respectively, which is much higher than the sample using nano-silver paste for die attach.
Abstract: Since a die-attach layer has significant impact on the thermal performance of a power module [1], its quality can be characterized using thermal performance. In this paper, a measurement system for thermal impedance is developed to evaluate three die-attach materials. Thanks to its high temperature sensitivity (10mV/0C), the gate-emitter voltage of an IGBT is used as the temperature-sensitive parameter. The power dissipation in the IGBT is maintained constant regardless of the junction temperature by a feedback loop. Experimental results show that the sample using sintered nano-silver for die-attach has 12.1% lower thermal impedance than the samples using SAC305 and SN100C solders. To check the degradation of the die-attachment, three samples using three die-attach materials were thermally cycled from -400C to 1250C. The experimental results show that after 500 cycles, the thermal impedance of SAC305 samples and SN100C samples is increased by 12.8% and 15% respectively, which is much higher than the sample using nano-silver paste for die-attach (increased by 4.1%).

51 citations

Journal ArticleDOI
TL;DR: Rodgers et al. as discussed by the authors evaluated the predictive accuracy of a commercial CFD code for both natural and forced convection heat transfer of single and multicomponent printed circuit boards (PCBs).
Abstract: The application of computational fluid dynamics (CFD) analysis for the thermal design of electronic systems has the potential to enable accurate solutions to be generated and quickly assessed. With the use of validated numerical models, numerical analysis can also be used to provide useful insights into heat transfer processes which could otherwise be difficult to characterize experimentally. However, the capabilities of the CFD tool need to be carefully evaluated so as to provide a degree of confidence in prediction accuracy, thereby minimizing the need to qualify thermal designs. Such an evaluation is presented in this paper, which represents the culmination of a benchmark study by Rodgers et al. [1999]. This overall study assesses the predictive accuracy of a commercial CFD code for both natural and forced convection heat transfer of single- and multicomponent printed circuit boards (PCBs). Benchmark criteria were based on both component junction temperature and component-PCB surface temperature profiles. In the context of the overall study, this paper brings these analyses together to provide a more comprehensive assessment of CFD predictive accuracy for component junction temperature. Additionally the validated numerical models are used to further investigate the sensitivity of component heat transfer to convective environment, both natural and forced, component position relative to the PCBs leading edge, impact of upstream aerodynamic disturbance, and the representation of PCB FR4 thermal conductivity. The significance of the listed variables is quantified by analyzing predicted component energy balances. Qualitative descriptions of the fluid flow fields obtained using a novel paint film evaporation technique are also provided in this study. Both analyses yield new insights of the heat transfer processes involved and sources of numerical error.

51 citations

Journal ArticleDOI
TL;DR: In this paper, the effect of power source parasitic inductance on dynamic current sharing is investigated for paralleled SiC mosfet s with Kelvin-source connection and some guidelines are provided for layout design and application.
Abstract: Parallel connection of silicon carbide (SiC) mosfet s is a popular solution for high-capacity applications. In order to improve the switching speed of paralleled SiC mosfet s, Kelvin-source connection is widely employed. However, the influences of asymmetric layout and unequal junction temperature on current sharing of paralleled SiC mosfet s with Kelvin-source connection are not clear. This article addresses the issue for the first time by theoretical analysis and experimental verifications. The mechanism of current imbalance resulting from asymmetric layout and unequal junction temperature in the case with Kelvin-source connection is comprehensively investigated. Then, some significant discoveries are obtained. The static current sharing performance can be affected by drain and power source parasitic inductance, which is seldom mentioned before. Besides, this article first points out that the effect of power source parasitic inductance on dynamic current sharing is dominant compared with other parasitic inductance. What is more, the thermal–electric analyzing results suggest that there is a risk of thermal runaway for paralleled SiC mosfet s with Kelvin-source connection at high switching frequency due to positively temperature-dependent dynamic current and switching losses. Based on the discoveries, some guidelines are provided for layout design and application of paralleled SiC mosfet s with Kelvin-source connection.

51 citations

Journal ArticleDOI
TL;DR: In this article, a two-stage thermoelectric module with one thermocouple in the second stage and several thermocouples in the first stage was investigated, and it was shown that the allocation of the junction temperature difference in the module, the length of thermocoupes and the number of thermouples can affect the cooling performance of the module.

51 citations

Proceedings Article
01 Jan 1984
TL;DR: In this paper, the authors discuss the mechanical and electrical integration of bypass diodes, starting with the array-level considerations which influence the selection of an implementation approach, and the concepts for mounting of these Diodes both internally within the module encapsulant and externally to the exposed rear surface of the module.
Abstract: Bypass diodes are often required to limit the potential for reverse voltage 'hot-spot' heating in high voltage arrays or in arrays that undergo periodic operation near the short-circuit point. In addition, when properly applied, bypass diodes can minimize the effect of shadowing and various internal module failures on the array energy output. This paper discusses the mechanical and electrical integration of bypass diodes beginning with the array-level considerations which influence the selection of an implementation approach. Concepts for the mounting of these diodes, both internally within the module encapsulant and externally to the exposed rear surface of the module, are described. Factors affecting the reliability of bypass diodes, including the control of junction temperature through adequate heat sinking and the derating of reverse voltage, are discussed.

51 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023118
2022277
2021233
2020287
2019334
2018303