Junction temperature

About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.

System and method for reducing temperature variation during burn in

Abstract: Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated with the integrated circuit is measured. A desired junction temperature of the integrated circuit is achieved by adjusting a body bias voltage of the integrated circuit. By controlling temperature of individual integrated circuits, temperature variation during burn-in testing can be reduced.

3D stacked microfluidic cooling for high-performance 3D ICs

Abstract: Cooling is a significant challenge for high-performance high-power 3D ICs. hi this paper, we describe the experimental evaluation of 3D ICs with embedded microfluidic cooling. Different architectures are experimentally evaluated ine hiding: 1) a memory-on-processor stack. 2) a processor-on-processor stack with equal power dissipation, and 3) a processor-on-processor stack with different power dissipation, hi all cases, embedded microfluidic cooling shows significant junction temperature reduction compared to air-cooling.

Modeling and analysis for thermal management in gallium oxide field-effect transistors

Abstract: Increased attention has been paid to the thermal management of β-Ga2O3 devices as a result of the large thermal resistance that can present itself in part due to its low intrinsic thermal conductivity. A number of die-level thermal management approaches exist that could be viable for thermal management. However, they have not been assessed for β-Ga2O3 devices exclusively. Here, we explore the limits of various die level thermal management schemes on a β-Ga2O3 metal–semiconductor field-effect transistor using numerical simulations. The effects of the various cooling approaches on the device channel temperature were comprehensively investigated, along with guidance for material selection to enable the most effective thermal solutions. Among various cooling strategies, double side cooling combined with a heat spreader used in the active region of the device can suppress the device thermal resistance to as low as 11 mm °C/W, achieving a maximum dissipated power density as high as 16 W/mm for a junction temperature limit of 200 °C. A multi-finger transistor thermal model was also developed to assess the potential of β-Ga2O3 devices for higher output power applications. Overall, this numerical study shows that it is possible to achieve high power β-Ga2O3 device operation with appropriate die-level thermal management solutions.

Thermal limitations of InP HBTs in 80- and 160-gb ICs

Abstract: Bipolar transistor scaling laws indicate that the dissipated power per unit collector-junction area increases in proportion to the square of the transistor bandwidth, increasing to /spl sim/10/sup 6/ W/cm/sup 2/ for InP heterojunction bipolar transistors (HBTs) designed for 160 Gb/s operation. A verified three-dimensional finite-element thermal model has been used to analyze the thermal resistance of InP in the context of 80 and 160 Gb/sup -1/ integrated circuits. The simulations show that the maximum temperature in the device can be significantly higher than the experimentally determined base-emitter junction temperature. Devices suitable for 160-Gb/s circuits will be thermally possible if the InGaAs etch-stop or contacting layer is removed from the subcollector.

A Pulse-Biasing Small-Signal Measurement Technique Enabling 40 MHz Operation of Vertical Organic Transistors.

Abstract: Organic/polymer transistors can enable the fabrication of large-area flexible circuits. However, these devices are inherently temperature sensitive due to the strong temperature dependence of charge carrier mobility, suffer from low thermal conductivity of plastic substrates, and are slow due to the low mobility and long channel length (L). Here we report a new, advanced characterization circuit that within around ten microseconds simultaneously applies an accurate large-signal pulse bias and a small-signal sinusoidal excitation to the transistor and measures many high-frequency parameters. This significantly reduces the self-heating and therefore provides data at a known junction temperature more accurate for fitting model parameters to the results, enables small-signal characterization over >10 times wider bias I–V range, with ~105 times less bias-stress effects. Fully thermally-evaporated vertical permeable-base transistors with physical L = 200 nm fabricated using C60 fullerene semiconductor are characterized. Intrinsic gain up to 35 dB, and record transit frequency (unity current-gain cutoff frequency, fT) of 40 MHz at 8.6 V are achieved. Interestingly, no saturation in fT − I and transconductance (gm − I) is observed at high currents. This paves the way for the integration of high-frequency functionalities into organic circuits, such as long-distance wireless communication and switching power converters.