Junction temperature

About: Junction temperature is a research topic. Over the lifetime, 5058 publications have been published within this topic receiving 58643 citations.

Forced convective interlayer cooling in vertically integrated packages

Abstract: The heat removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters les 200 mum. An experimental investigation with uniform and double-side heat flux at Reynolds numbers les 1000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. Parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mum and fluid structure heights of 100 to 200 mum were tested. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin inline structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks with a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from >200 W/cm2 at 1 cm2 and >50 mum interconnect pitch to <100 W/cm2 at 4 cm2.

Thermal management system for high performance PowerPC/sup TM/ microprocessors

Abstract: Thermal management is an important design issue in high-performance, low-power portable computers If the computer system is designed for worst-case processor power dissipation and environmental operating conditions, it carries an area and cost penalty for the system designer The next-generation PowerPC/sup TM/ microprocessor includes a thermal assist unit (TAU) comprised of an on-chip thermal sensor and associated logic The TAU monitors the junction temperature of the processor and dynamically adjusts processor operation to provide maximum performance under changing environmental conditions The TAU is used in conjunction with other low-power features such as dynamic power management, instruction cache throttling and static low-power modes to provide comprehensive power and thermal management This paper describes the implementation of the TAU and presents its characterization and operating data from first silicon

Advanced Accelerated Power Cycling Test for Reliability Investigation of Power Device Modules

Abstract: This paper presents an apparatus and methodology for an advanced accelerated power cycling test of insulated-gate bipolar transistor (IGBT) modules. In this test, the accelerated power cycling test can be performed under more realistic electrical operating conditions with online wear-out monitoring of tested power IGBT module. The various realistic electrical operating conditions close to real three-phase converter applications can be achieved by the simple control method. Further, by the proposed concept of applying the temperature stress, it is possible to apply various magnitudes of temperature swing in a short cycle period and to change the temperature cycle period easily. Thanks to a short temperature cycle period, test results can be obtained in a reasonable test time. A detailed explanation of apparatus such as configuration and control methods for the different functions of accelerated power cycling test setup is given. Then, an improved in situ junction temperature estimation method using on-state collector–emitter voltage $V_{{\rm CE}\_{\rm ON}}$ and load current is proposed. In addition, a procedure of advanced accelerated power cycling test and test results with 600 V, 30 A transfer molded IGBT modules are presented in order to verify the validity and effectiveness of the proposed apparatus and methodology. Finally, physics-of-failure analysis of tested IGBT modules is provided.

A noncontact method for determining junction temperature of phosphor-converted white LEDs

Abstract: The goal of this study was to develop a non-contact method for determining the junction temperature of phosphor-converted white LEDs as a first step toward determining the useful life of systems using white LEDs. System manufacturers generally quote the same life values for their lighting systems that the LED manufacturers estimate for a single LED. However, the life of an LED system can be much different compared with the life of an LED tested under ideal conditions because system packaging can affect system life. Heat at the pn-junction is one of the key factors that affect the degradation rate, and thus the useful life, of GaN-based white LEDs. The non-contact method described in this manuscript, combined with LED degradation rates, can be used to predict white-LED system life without affecting the integrity of the lighting system or submitting it to long-term life tests that are time-consuming. Different types of LED packages would have different degradation mechanisms. Therefore, as a first step this study considered only the 5mm epoxy encapsulated GaN+YAG Cerium phosphor white LED. The method investigated here explored whether the spectral power distribution (SPD) of the white LED could provide the necessary information to estimate LED junction temperature. Based on past studies that have shown that heat affects the radiant energy emitted by the InGaN blue LED and the YAG Cerium phosphor differently, the authors hypothesized that the ratio of the total radiant energy (W) to the radiant energy within the blue emission (B) would be proportional to the junction temperature. Experiments conducted in this study verified this hypothesis and showed that the junction temperature can be measured non-invasively through spectral measurements.