Showing papers on "Latency (engineering) published in 1993"

GABA shapes a topographic organization of response latency in the mustache bat's inferior colliculus

Abstract: Many neurons in the auditory forebrain of the mustache bat act as coincidence detectors for signals separated in time by up to 20 msec. Differences in path lengths cannot adequately explain how the nervous system delays one signal relative to the other to such a large degree. Several researchers have proposed that an inhibitory mechanism might account for long delays, but it has not been known where these delays are created. Previous studies, using a variety of mammals, have reported that the inferior colliculus contains some cells with much longer latencies than those of cells in lower auditory centers, suggesting that the inferior colliculus might be the site where long delays are generated. We characterized the latencies of cells in the 60 kHz contour of the mustache bat inferior colliculus and examined how GABAergic inhibition affected the latencies of those cells. Evaluations of the influence of GABA were made by documenting changes in response latency that occurred when GABAergic inputs were reversibly blocked by iontophoretic application of the GABAA antagonist bicuculline. Prior to bicuculline application, latencies varied over a wide range among the population of cells and we observed a pattern of latency changes with dorsoventral location. The pattern was that the population of neurons in the dorsal regions of the inferior colliculus had a wide range of latencies while the population in more ventral regions had progressively narrower latency ranges. Thus, while some cells at each depth had comparably short latencies, the average latency of the population at a given depth was long in the dorsal inferior colliculus and became progressively shorter ventrally. The same characteristic distribution of latencies and pattern of latency changes with depth were observed for cells that had different aural preferences, different rate-intensity functions, and different discharge patterns, suggesting that latency is an important organizational feature of the inferior colliculus. Bicuculline substantially shortened latency in about half of the cells studied, and it dramatically altered the pattern of latency changes with depth. These results suggest that GABA normally lengthens response latencies and creates a dorsoventral grading of delays in the inferior colliculus. This wide range of latencies could provide the large latency differences necessary for the coincidence detectors in the medial geniculate body tuned to signals separated by up to 20 msec.

Variable latency cut through bridge for forwarding packets in response to user's manual adjustment of variable latency threshold point while the bridge is operating

Abstract: A variable latency cut through bridge (210) for selectively forwarding data packets (10) within a network (310) of computers (312), the variable latency cut through bridge (210) employing a variable latency bridging method wherein the latency factor of the variable latency cut through bridge (210) is set according to the position of a variable threshold point (428). The variable threshold point (428) is optionally set to within a rapid drop off portion (520) of a probability line (514) describing the probability that the data packet (10) is bad as a function of the amount of the packet (10) which has been examined within the variable latency cut through bridge (210).

Effect of Histamine on Memory Retrieval in Old Rats

Abstract: Effects of intracerebroventricular (i.c.v) injection of histamine (Hi) and its related compounds on prolongation of the response latency ensuing after a long interruption of learning were studied by testing the active avoidance response in old rats. After Hi application at doses of 50 and 100 ng, the response latency became significantly shorter than that determined in the pre-injection periods, suggesting that Hi facilitates memory retrieval in old rats. H1-agonists, 2-methylHi and 2-thiazolylethylamine, effected a dose-related shortening of response latency as seen after Hi application, whereas H2-agonists, 4-methylHi and impromidine, failed to prompt the response latency. Simultaneous i.c.v. injection of pyrilamine, a H1-antagonist and Hi abolished the Hi-induced shortening of response latency. Furthermore, intraperitoneal administration of histidine at doses of 200 and 500 mg/kg significantly shortened the response latency. Neither (R)-α-methylHi nor thioperamide caused a significant effect indicating that H3-receptor may not be involved in Hi-induced facilitation of memory retrieval. Based on these findings, it may be concluded that Hi takes an active part in facilitating memory recall via H1-receptor in old rats.

Effects of simulated high altitude exposure on long-latency event-related brain potentials and performance.

Abstract: The N100, P200, N200 and P300 components of the auditory event-related potential were recorded from 10 male subjects at 0900, 1600, and 1830 hours at sea level and again following a rapid ascent to simulated 4300 m altitude. Amplitude and latency of components, ear oximetry, and concurrent performance measures (reaction time and counting errors) were assessed. Amplitude of P300 decreased, while P300 latency and reaction time increased, following ascent to altitude. However, the time course of altitude effects differed for amplitude versus latency. Components N100, P200, N200, and counting errors were unaffected by altitude. The results indicate that central measures of cognitive capacities are differentially sensitive to high altitude. The time course of altitude effects on P300 amplitude versus P300 latency suggests that the two measures reflect different aspects of a response to hypobaric hypoxia exposure.

Controlling interindividual differences in the unconditioned response to amphetamine in the study of environment-dependent sensitization.

Abstract: Two subgroups of rats selected on the basis of their emergence latency in a light-dark box test were shown to exhibit significantly different unconditioned responses to d-amphetamine (AMPH, 1 mg/kg). The rats presenting a low latency to emerge from the dark side (LL subgroup) responded more to AMPH

Architecture of highly parallel AP1000 computer

Abstract: This paper describes the architectural features of the AP1000 message-passing computer. The architecture is designed to speed up barrier synchronization, data distribution and collection, broadcasting, and message handling. In recent message-passing computers, the most significant communication overhead is that associated with interrupt processing and message assembly/disassembly, because the adoption of new routing schemes has reduced the network latency. It is important for a fast message-passing computer to reduce not only network latency but also message handling latency. Although broadcasting, data distribution and collection, and barrier synchronization are necessary functions in many applications, these functions were slow in prior message-passing computers because each of these functions were simulated by many one-to-one communications. The AP1000 has three independent communication networks and message handling hardwares, fast barrier synchronization capabilities, and data distribution and collection hardware to speed up those functions.

Method and apparatus for enabling a computer system to adjust for latency assumptions

Abstract: A method and system are disclosed which allow a computer program to execute properly in object code compatible processing systems which have latencies different from those with which the program was created or compiled This resulting compatibility of the computer program is achieved because the invention protects the precedence of operations within the computer program using latency assumptions which were used when creating the computer program When the computer program is created, latency assumption information is efficiently provided within the computer program Thereafter, when the computer program is executed, it is able to advise the processing system of the latency assumptions with which it was created Various ways are described in which the processing system can utilize the latency assumptions when executing the computer program so as to ensure compatibility

NPCPL : Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs

Abstract: High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both of t h e m simultaneously. We propose a Normal Process Complementary Pass Transistor Logic (NPCPL) which can be used as a universal logic to provide finest grain pipelining without affecting overall latency o r increasing the area. It does n o t require any special process steps and hence, can be Tealised in a normal process technology as against the CPL proposed by Yano et al [2] which uses threshold voltage adjustment of selected devices. The design procedure is described for (a)low latency, (b)high throughput and (c)low area requirements. In addition to the various advantages, it is envisioned that NPCPL designs can also be used to build ultra-high speed pipelined system without pipelining latches, viz., wave pipelined digital systems, where the throughput achievable is beyond that permitted by the delay of a pipeline stage.

A quantitative technique for the study of the latency of Aujeszky virus

Abstract: Summary: Latency represents a challenge for any herpesvirus vaccine. Vaccines could differ in their ability to minimize latency of Pseudorabies virus (PRV). To study this possibility, a quantitative and differential PRV-specific polymerase chain reaction (PCR) was developed by the authors. Efficiency of amplification in different tubes is measured by co-amplificat ion with the viral targets (either gI or gp50 genes) of the porcine gene nuclear factor 1. The criteria used to select this approach to a quantitative PCR, as well as for the selection of the standard, are discussed. The amplified products are measured by Southern blot or, alternatively, high performance liquid chromatography. Sensitivity and reproducibility of the technique are evaluated. The ability of this technique to discriminate between the level of latency established by two different PRV strains in trigeminal ganglia is also evaluated. Using this technique, the authors are currently studying whether different vaccines could possess differing levels of ability to minimize, by interference, establishment of wild-type latency.

Latency in the inositol lipid transduction pathway: the role of cellular events in responses to thyrotropin-releasing hormone in Xenopus oocytes

Abstract: To dissect the cellular events responsible for the prolonged latency of the response to thyrotropin-releasing hormone (TRH) in Xenopus oocytes we interfered with different steps of the signal transduction pathway. Preincubation of oocytes with cis-vaccenic acid (a membrane-fluidizing agent) shortened the latency, suggesting a contribution of membranal processes. TRH-induced depletion of cellular calcium stores prolonged latency (up to threefold), which returned to control levels upon repletion of the stores. Injection of D-2,3-diphosphoglycerate (PGA), which inhibits inositol (1,4,5)-trisphosphate (InsP3) dephosphorylation, alone evoked a small, prolonged depolarizing current and significantly shortened the latency of the response to TRH. Injection of guanosine 5'-O-(2-thiodiphosphate) (GDP beta S), which inactivates guanine nucleotide-binding regulatory proteins, decreased the amplitude of the response and increased latency. Injection of guanosine 5-O-(3-thiotriphosphate) (GTP gamma S) immediately before the challenge with TRH did not shorten the latency of the response. Decreasing the effective receptor density with chlordiazepoxide, an antagonist of the TRH receptor, resulted in an extension of latency, whereas the expression of a large number of TRH receptors by injection of RNA transcribed from cloned receptor DNA (10-100 ng/oocyte) shortened the latency to below 2 s. Our results suggest that the latency of the response to TRH reflects the activation of a late step in the signal transduction sequence, most likely the release of calcium by InsP3. We propose that this process is kinetically controlled by an early rate-limiting event, involving the activation of a guanine nucleotide-binding protein by the TRH receptor.

Handling qualities effects of display latency

Abstract: Display latency is the time delay between aircraft response and the corresponding response of the cockpit displays. Currently, there is no explicit specification for allowable display lags to ensure acceptable aircraft handling qualities in instrument flight conditions. This paper examines the handling qualities effects of display latency between 70 and 400 milliseconds for precision instrument flight tasks of the V-22 Tiltrotor aircraft. Display delay effects on the pilot control loop are analytically predicted through a second order pilot crossover model of the V-22 lateral axis, and handling qualities trends are evaluated through a series of fixed-base piloted simulation tests. The results show that the effects of display latency for flight path tracking tasks are driven by the stability characteristics of the attitude control loop. The data indicate that the loss of control damping due to latency can be simply predicted from knowledge of the aircraft's stability margins, control system lags, and required control bandwidths. Based on the relationship between attitude control damping and handling qualities ratings, latency design guidelines are presented. In addition, this paper presents a design philosophy, supported by simulation data, for using flight director display augmentation to suppress the effects of display latency for delays up to 300 milliseconds.

Accurate computation of field reject ratio based on fault latency

Abstract: It is shown that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. The authors model the detection of a fault by an input test vector as a random event. However, the detection of a fault may be delayed for various reasons: the fault may be detectable only by application of a sequence of vectors or it may not have been targeted until later. In the statistical model, a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of the detection probability, the fault cannot be detected by a vector sequence shorter than its latency. The circuit is characterized by the joint distribution of latency and detection probability over all faults. This distribution, obtained by applying the Bayes' rule to the actual test data, allows computations the field reject ratio. The sensitivity of this approach to variations in the measured parameters is also investigated. >

Abnormal short-latency somatosensory evoked potentials in two patients with carbohydrate-deficient glycoprotein syndrome

Abstract: Carbohydrate-deficient glycoprotein (CDG) syndrome is an autosomal recessive disorder characterized by mental retardation, ataxia, polyneuropathy, hepatopathy during infancy, growth retardation and multiple carbohydate-deficient serum glycoproteins (1, 2) . Recently, we have reported three Japanese patients with CDG syndrome ( 3 ) . Patellar reflexes in the two oldest patients were difficult to elicit. In the oldest patient (patient No. l ) , sensory and motor nerve conduction velocities (NCVs) were severely delayed, but those in the

New Disk Scheduling Algorithms for Reduced Rotational Latency

Abstract: Disk arm scheduling algorithms have been studied for many years to increase disk I/O performance. Most of the disks by the early 1980’s are characterized as a linear seek time and their seek time is responsible for the most time of disk access. So, the existing disk scheduling algorithms have focused on the reduction of the average seek distance. Seek time has improved greatly and today’s disks usually have nonlinear seek time characteristics, whereas the rotation speed has been steady at the 3600 RPM. So, it is of value to reduce average rotational latency. In this paper we propose two disk scheduling algorithms, i.e. Shortest Rotational Latency First(SRLF) and Shortest Access Tie Fist(SATF) for reduced rotational latency. SRLF services first a request with the shortest expected rotational latency and SATF services first a request with the shortest expected access time. We analyze the expected access time of the request serviced first by each of SSTF and SRLF under the uniform cylinder access. We evaluated the response time of SSTF, SRLF, and SATF through the simulations under the uniform and localized cylinder access. The results of the analysis and simulations show that the algorithms proposed in this paper are more efficient than SSTF which is known for the fastest response time.

Control of hybrid packet rings

Abstract: A hybrid ring network is disclosed having stations capable of transmitting and receiving packet and isochronous data. The ring stations include a latency adjustment buffer (LAB) which stores arriving packet data in one random access memory (PBUF) and both arriving packet and isochronous data in a separate random access memory (IBUF). For retransmission over the ring, packet data is read out only from the PBUF in accordance with the packet's retransmission priority. A LAB may be employed at a slave station and may be pre-programmed with a sufficient latency to compensate for an anticipated insertion or removal of a lobe, without changing the total latency of the ring. When a LAB is employed at a cycle master station the latency of the LAB is controlled by the total ring delay.

Primary display latency criteria based on flying qualities and performance data

Abstract: With a pilots' increasing use of visual cue augmentation, much requiring extensive pre-processing, there is a need to establish criteria for new avionics/display design. The timeliness and synchronization of the augmented cues is vital to ensure the performance quality required for precision mission task elements (MTEs) where augmented cues are the primary source of information to the pilot. Processing delays incurred while transforming sensor-supplied flight information into visual cues are unavoidable. Relationships between maximum control system delays and associated flying qualities levels are documented in MIL-F-83300 and MIL-F-8785. While cues representing aircraft status may be just as vital to the pilot as prompt control response for operations in instrument meteorological conditions, presently, there are no specification requirements on avionics system latency. To produce data relating avionics system latency to degradations in flying qualities, the Navy conducted two simulation investigations. During the investigations, flying qualities and performance data were recorded as simulated avionics system latency was varied. Correlated results of the investigation indicates that there is a detrimental impact of latency on flying qualities. Analysis of these results and consideration of key factors influencing their application indicate that: (1) Task performance degrades and pilot workload increases as latency is increased. Inconsistency in task performance increases as latency increases. (2) Latency reduces the probability of achieving Level 1 handling qualities with avionics system latency as low as 70 ms. (3) The data suggest that the achievement of desired performance will be ensured only at display latency values below 120 ms. (4) These data also suggest that avoidance of inadequate performance will be ensured only at display latency values below 150 ms.

Real-time concurrency control with analytic worst-case latency guarantees

Abstract: Meeting hard deadlines while also ensuring the integrity of shared data is a diicult problem in real-time systems design. We discuss the key diierences between database con-currency control and concurrency control for hard-real-time systems and describe an approach to adapting advanced con-currency control techniques to systems requiring analytic worst-case latency guarantees. We describe an example con-currency control technique, implementable with simple and low-overhead algorithms and data structures, which completely avoids interference between queries and updaters. This report ooers a high-level overview and introduction to the problem and approach. Details are provided in other reports SY92a, SY92b].

Method for emitting light which does not substantially delay the latency of P100 wave in human VEP

Abstract: Disclosed is a lighting device to emit a light which substantially does not delay the latency of P100 wave in human VEP. Such a light hardly causes eyestrain when used in illumination. This renders the lighting device very useful in various illuminations directed to retaining healthy eyes.

Models of Communication Latency in Shared Memory Multiprocessors

Abstract: We evaluate various mechanisms for data communication in large-scale shared memory multiprocessors. Data communication involves both data transmission and synchronization, resulting in the transfer of data between computational threads. We use simple analytical models to evaluate the communication latency for each of the mechanisms. The models show that efficient and opportunistic synchronization is the most important determinant of latency, followed by efficient transmission. Producer-initiated mechanisms, in which data is sent by its producer as it is produced, generally achieve lower latencies than consumer-initated mechanisms, in which data is retrieved as and when it is needed.

Lighting device for emitting light without substantially delaying the latency of P300 wave in human event related potential

Abstract: Disclosed is a lighting device to emit a light which substantially does not delay the latency of P300 wave in human ERP. Such a light hardly reduces human recognition and judgement when used in illumination. This renders the lighting device very useful in various illuminations directed to improve the efficiency and accuracy in visual tasks.

Avoiding and tolerating latency in large-scale next-generation shared-memory multiprocessors

Abstract: A scalable solution to the memory-latency problem is necessary to prevent the large latencies of synchronization and memory operations inherent in large-scale shared-memory multiprocessors from reducing high performance. We distinguish latency avoidance and latency tolerance. Latency is avoided when data is brought to nearby locales for future reference. Latency is tolerated when references are overlapped with other computation. Latency-avoiding locales include: processor registers, data caches used temporally, and nearby memory modules. Tolerating communication latency requires parallelism, allowing the overlap of communication and computation. Latency-tolerating techniques include: vector pipelining, data caches used spatially, prefetching in various forms, and multithreading in various forms. Relaxing the consistency model permits increased use of avoidance and tolerance techniques. Each model is a mapping from the program text to sets of partial orders on program operations; it is a convention about which temporal precedences among program operations are necessary. Information about temporal locality and parallelism constrains the use of avoidance and tolerance techniques. Suitable architectural primitives and compiler technology are required to exploit the increased freedom to reorder and overlap operations in relaxed models.

Empirical study of latency hiding on a fine-grain parallel processor

Abstract: Latency associated with memory accesses and process communications are one of the most difficult obstacles in constructing a practical massively parallel system. So far, two approaches to hide latencies have been proposed. They are prefetching and multi-threading. An instruction-level data-driven computer is an ideal test-bed for evaluating these latency hiding methods because prefetching and multi-threading are naturally implemented in an instruction-level data-driven computer as unfolding and concurrent execution of multiple contexts. This paper evaluates latency hiding methods on SIGMA-1, a dataflow supercomputer developed in Electrotechnical Laboratory. As a result of evaluation, these methods are effective to hide static latencies but not effective to hide dynamic latencies. Also, concurrent execution of multiple contexts is more effective than prefetching.