Showing papers on "Latency (engineering) published in 1999"

Effects of network characteristics on human performance in a collaborative virtual environment

Abstract: We assessed the effects of network latency and jitter on a cooperative teleoperation task in a collaborative virtual environment. Two remote partners worked together to manipulate shared virtual objects over a network. The task was to minimize the time to transfer a ring through one of four paths with the least number of collisions. The performance of human subjects was measured and analyzed quantitatively as a function of network latency: 10 and 200 msec delays with and without jitter. Jitter had the greatest impact on coordination performance when the latency was high and the task was difficult. These results are discussed in light of current and future CVE tasks.

A methodology for correct-by-construction latency insensitive design

Abstract: In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires. Given a synchronous specification of a design, we generate a functionaly equivalent synchronous implementation that can tolerate arbitrary communication latency between latches. By using latches we can break a long wire in short segments which can be traversed while meeting a single clock cycle constraint. The overall goal is to obtain a design that is robust with respect to delays of long wires, in a shorter time by reducing the multiple iterations between logical and physical design, and with performance that is optimized with respect to the speed of the single components of the design. In this paper we describe the details of the proposed methodology as well as report on the latency insensitive design of PDLX, an out-of-order microprocessor with speculative-execution.

Technique for measuring round-trip latency to computing devices requiring no client-side proxy presence

Abstract: A method, system, and computer-readable code for measuring network latency between a client computer and a server machine without requiring any additional software on the client. Network latency is a measurement that reflects the network round trip delay between a client machine and a server machine. The present invention defines a novel technique for gathering latency information. This information may be used in a variety of ways (such as making policy decisions that may limit the amount of data sent over a communications path due to detection of high latency in the network).

Load Latency Tolerance in Dynamically Scheduled Processors.

Abstract: This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our simulations use flexible load completion policies instead of a fixed memory hierarchy that dictates the latency. Although our policies delay load completion as long as possible, they produce performance (instructions committed per cycle (IPC)) comparable to an ideal memory system where all loads complete in one cycle. Our measurements reveal that to produce IPC values within 8% of the ideal memory system, between 1% and 62% of loads need to be satisfied within a single cycle and that up to 84% can be satisfied in as many as 32 cycles, depending on the benchmark and processor configuration. Load latency tolerance is largely determined by whether an unpredictable branch is in the load's data dependence graph and the depth of the dependence graph. Our results also show that up to 36% of all loads miss in the level one cache yet have latency demands lower than second level cache access times. We also show that up to 37% of loads hit in the level one cache even though they possess enough latency tolerance to be satisfied by lower levels of the memory hierarchy.

Latency analysis in epidemiologic studies of occupational exposures : Application to the colorado plateau uranium miners cohort

Abstract: Background Latency effects are an important factor in assessing the public health implications of an occupational or environmental exposure. Usually, however, latency results as described in the literature are insufficient to answer public health related questions. Alternative approaches to the analysis of latency effects are warranted. Methods A general statistical framework for modeling latency effects is described. We then propose bilinear and exponential decay latency models for analyzing latency effects as they have parameters that address questions of public health interest. Methods are described for fitting these models to cohort or case-control data; statistical inference is based on standard likelihood methods. Application A latency analysis of radon exposure and lung cancer in the Colorado Plateau uranium miners cohort was performed. We first analyzed the entire cohort and found that the relative risk associated with exposure increases for about 8.5 years and thereafter decreases until it reaches background levels after about 34 years. The hypothesis that the relative risk remains at its peak level is strongly rejected (P > 0.001). Next, we investigated the variation in the latency effects over subsets of the cohort based on attained age, level and rate of exposure, and smoking. Age was the only factor for which effect modification was demonstrated (P > 0.014). We found that the decline in effect is much steeper at older ages (60> years) than younger. Conclusion The proposed methods can provide much more information about the exposure–disease latency effects than those generally used. Am. J. Ind. Med. 35:246–256, 1999. © 1999 Wiley-Liss, Inc.

Semiconductor memory asynchronous pipeline

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Cost calculation in load balancing switch protocols

Abstract: A method for computing cost information associated with a port of a switch in a network of switches. Cost information is computed as a port load factor: a ratio of port latency over available throughput. Port latency is determined as the depth of a queue associated with the port divided by the speed of the port. Available throughput is determined as the speed of the slowest port on a given path associated with the port in question. Preferably, the queue depth is measured in bits and the port speed and available throughput are measured in bits per second. Further, in the preferred embodiment, port latency is computed as a weighted average as ((15×previous latency)+current latency)/16. A higher value for the port load factor indicates a port which is more heavily loaded. The load factor is therefore useful in load balancing among the ports of switches and paths associated therewith.

Effect of Increasing System Latency on Localization of Virtual Sounds

Abstract: In a virtual acoustic environment, the total system latency (TSL) refers to the time elapsed from the transduction of an event or action, such as movement of the head, until the consequences of that action cause the equivalent change in the virtual sound source. This paper reports on the impact of increasing TSL on localization accuracy when head motion is enabled. Five subjects estimated the location of 12 virtual sound sources (individualized head-related transfer functions) with latencies of 33.8, 100.4, 250.4 or 500.3 ms in an absolute judgement paradigm. Subjects also rated the perceived latency on each trial. The data indicated that localization was generally accurate, even with a latency as great as 500 ms. In particular, front-back confusions were minimal and unaffected by latency. Mean latency ratings indicated that latency had to be at least 250 ms to be readily perceived. The fact that accuracy was generally comparable for the shortest and longest latencies suggests that listeners are able to ignore latency during active localization, even though delays of this magnitude produce an obvious spatial “slewing” of the source such that it is no longer stabilized in space.

Herpes Simplex Virus Latency-Associated Transcript Encodes a Protein Which Greatly Enhances Virus Growth, Can Compensate for Deficiencies in Immediate-Early Gene Expression, and Is Likely To Function during Reactivation from Virus Latency

Abstract: Herpes simplex virus types 1 and 2 (HSV1 and HSV2) enter and reactivate from latency in sensory neurons, although the events governing these processes are little understood. During latency, only the latency-associated transcripts (LATs) are produced. However, although the LAT RNAs were described approximately 10 years ago, their function remains ambiguous. Mutations affecting the LATs have minimal effects other than a small reduction in establishment of and reactivation from latency in some cases. Mutations in putative LAT-contained open reading frames (ORFs) have so far shown no effect. The LATs consist of a large species from which smaller (approximately 2 kb), nuclear, nonlinear LATs which are abundant during latency are spliced. Thus, translation of ORFs in these smaller LATs would not usually be expected to be possible, and if expressed at all, their expression might be tightly regulated. Here we show that deregulated expression of the largest HSV1 2-kb LAT-contained ORF in various cells of neuronal and nonneuronal origin greatly enhances virus growth in a manner specific to HSV1-the HSV1 LAT ORF has no effect on the growth of HSV2. Similar results of enhanced growth were found when the HSV1 LAT ORF was constitutively expressed from within the HSV1 genome. The mechanism of LAT ORF action was strongly suggested to be by substituting for deficiencies in immediate-early (IE) gene expression (particularly ICP0), because deregulated LAT ORF expression, as well as enhancing wild-type virus growth, was also found to allow efficient growth of viruses with mutations in ICP0 or VMW65. Such viruses otherwise exhibit considerable growth defects. IE gene expression deficiencies are often the block to productive infection in nonpermissive cells and are also evident during latency. These results, which we show to be protein- rather than RNA-mediated effects, strongly suggest a function of the tightly regulated expression of a LAT ORF-encoded protein in the reactivation from HSV latency.

Method and apparatus for gap count determination

Abstract: A method and apparatus for determining a gap count for a serial bus network (100) is described. A round-trip delay time for transmitting a packet from a first leaf node to a second leaf node and back over a communication path between the nodes for each pair of leaf nodes (302) in the network is determined. A maximum round-trip delay time (304) for each communication path is calculated. A node latency delay time (306) for each leaf node in the network is determined. A longest maximum round-trip delay time (308) and a longest node latency delay time is selected for the network, and a gap count (310) is calculated using the selected times.

Recurrent nasopharyngeal carcinoma: the puzzles of long latency

Abstract: Purpose: To study the peculiar characteristics of relapses with long latency following radical treatment for nasopharyngeal carcinoma. Methods and Materials: 847 patients with nasopharyngeal recurrence were retrospectively studied, focusing on the independent effects of latency on different outcome aspects and its relationship with other prognostic factors. Results: The proportion of recurrence with latency p p Conclusions: Nasopharyngeal recurrence with long latency showed different natural behavior: the prognosis was significantly better due to lower risk of distant failure.

Latency Insensitive Protocols

Abstract: The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of Intellectual Properties. Latency insensitive designs are synchronous distributed systems and are realized by assembling functional modules exchanging data on communication channels according to an appropriate protocol. The goal of the protocol is to guarantee that latency insensitive designs composed of functionally correct modules, behave correctly independently of the wire delays. A latency-insensitive protocol is presented that makes use of relay stations buffering signals propagating along long wires. To guarantee correct behavior of the overall system, modules must satisfy weak conditions. The weakness of the conditions makes our method widely applicable.

Discrimination of Changes of Latency during Voluntary Hand Movement of Virtual Objects

Abstract: Eight subjects' abilities to detect changes in system latency during voluntary lateral hand movement of virtual objects were studied in an immersing virtual environment. A two-alternative forced choice procedure was used in which discrimination of latency was studied with respect to three reference latencies: 27, 94, and 194 msec. Results show that subjects are able to reliably detect changes definitely less than 33 msec and probably less than 16.7 msec. Strikingly, for the short latencies we examined, subjects' ability to detect latency changes does not depend upon the base latency we used as a reference. Thus, the discrimination we studied does not appear to follow Weber's law and may provide evidence for quick adaptation to the reference latencies used.

A real-time low-latency hardware light-field renderer

Abstract: This paper describes the design and implementation of an architecture for interactively viewing static light fields with very low latency. The system was deliberately over engineered to specifications much tighter than expected necessary to eliminate perceptible latency. This allowed us to relax the specifications to the point at which human users began to detect latency artifacts. We found empirically that when interacting with a light field, human users began to notice latency artifacts when the total system latency is approximately 15 ms. Although the architecture may not be used in practice, this result should prove fundamental for designers of future interactive graphics systems. CR

Circuit arrangement and method with state-based transaction scheduling

Abstract: A data processing system (10), circuit arrangement, and method rely on state information to prioritize certain transactions relative to other transactions when scheduling transactions in a data processing system (10). In one implementation, as a result of the recognition that in many shared memory systems cached data having a modified state is accessed more frequently than cached data having a non-modified state, transactions associated with modified cached data are prioritized (100, 120) relative to transactions associated with non-modified cached data, thereby reducing the latency of such modified transactions. Any concurrent increase in latency for non-modified transactions is more than offset by the decreased latency of modified transactions, resulting in an overall reduction in system latency.

Low Latency, Low Loss, Scalable Throughput (L4S) Internet Service: Architecture

Abstract: This document describes the L4S architecture for the provision of a new service that the Internet could provide to eventually replace best efforts for all traffic: Low Latency, Low Loss, Scalable throughput (L4S). It is becoming common for _all_ (or most) applications being run by a user at any one time to require low latency. However, the only solution the IETF can offer for ultra-low queuing delay is Diffserv, which only favours a minority of packets at the expense of others. In extensive testing the new L4S service keeps average queuing delay under a millisecond for _all_ applications even under very heavy load, without sacrificing utilization; and it keeps congestion loss to zero. It is becoming widely recognized that adding more access capacity gives diminishing returns, because latency is becoming the critical problem. Even with a high capacity broadband access, the reduced latency of L4S remarkably and consistently improves performance under load for applications such as interactive video, conversational video, voice, Web, gaming, instant messaging, remote desktop and cloud-based apps (even when all being used at once over the same access link). The insight is that the root cause of queuing delay is in TCP, not in the queue. By fixing the sending TCP (and other transports) queuing latency becomes so much better than today that operators will want to deploy the network part of L4S to enable new products and services. Further, the network part is simple to deploy - incrementally with zero-config. Both parts, sender and network, ensure coexistence with other legacy traffic. At the same time L4S solves the long- recognized problem with the future scalability of TCP throughput. This document describes the L4S architecture, briefly describing the different components and how the work together to provide the aforementioned enhanced Internet service.

Discrimination of changes in latency during head movement

Abstract: Human users of virtual environments (VE) are disturbed by system latency which reduces interactivity, user dexterity, and speed Because latencies in VEs arise from rendering, switching and transmissions delays, they will continue to persist in systems involving satellite or space communication links even as computing speeds increase Our previous work has focused on the precision, stability, efficiency and complexity of operator interaction in latency-plagued systems (eg, Ellis, Breant, Menges, Jacoby, & Adelstein, 1997) But there has been relatively little work on users' subjective response to changes in system latency which could cue impending degraded performance and also disturb users' sense of immersion in "virtual" tasks (see Uno & Slater, 1997) In particular, operators' psychophysical functions describing sensitivity to detection of the visual consequences of latency change have not been measured We have measured these functions for the first time for head movement while users view nearby virtual objects

Latency and networking aspects of adaptive modems over slow indoors Rayleigh fading channels

Abstract: Adaptive modulation exploits the time-variant channel capacity fluctuation of fading channels using a range of different modem modes. Specifically, no information is transmitted when the instantaneous channel signal-to-noise ratio (SNR) is low, and, hence, during this period the data must be buffered, which results in delay or latency, When the instantaneous channel quality improves, 2-, 4-, 16-, and 64-level modem modes are invoked, which allows the transmission buffer to be emptied. It is shown that channel capacity gains are achieved at the cost of some latency penalty. The latency is quantified in this treatise and mitigated by frequency hopping or statistical multiplexing. The latency is increased when either the mobile speed or the channel SNR are reduced, since both of these result in prolonged low instantaneous SNR intervals. It is demonstrated that as a result of the proposed measures, typically more than 4-dB SNR reduction is achieved by the proposed adaptive modems in comparison to the conventional benchmark modems employed.

Influence of control loop latency on time-delayed feedback control.

Abstract: As realized recently, the success of delayed feedback control methods may be significantly restricted by control loop latency, i.e., by an additional delay which acts on the control force. We show within a linear stability analysis that such a limitation is caused by the shift of frequency splitting points. Our analytical results are in good quantitative agreement with numerical ``exact'' calculations of the Toda oscillator and with data from an electronic circuit experiment.

Integration of multi-stage execution units with a scheduler for single-stage execution units

Abstract: A superscalar processor includes a central scheduler for multiple execution units. The scheduler presumes operations issued to a particular execution unit all have the same latency, e.g., one clock cycle, even though some of the operations have longer latencies, e.g., two clock cycles. The execution unit that executes the operations having with longer than expected latencies, includes scheduling circuitry that holds up particular operation pipelines when operands required for the pipelines will not be valid when the scheduler presumes. Accordingly, the design of the scheduler can be simplified and can accommodate longer latency operations without being significantly redesigned for the longer latency operations.

Hit and False-Positive Rates for the Middle Latency Response in Patients with Central Nervous System Involvement

Abstract: We sought to determine the test efficiency of the middle latency evoked response for identifying or differentiating subjects with and without central nervous system (CNS) involvement. Receiver operating characteristic curves were established for hit and false-positive rates for 26 subjects with CNS lesions and 26 control subjects matched for age and hearing sensitivity . The lesions involved but were not limited to the auditory regions of the CNS . Middle latency evoked response latency and amplitude measurements were made for the Na and Pa waves recorded at C3 and Ca electrode sites following stimulation of the left and right ears. Intrasubject comparisons were made for ipsilateral and contralateral stimulation/recording conditions. Amplitude measures were superior to latency measures . For amplitude, percentage differences from contralateral comparisons proved to be the most sensitive and specific measure . The clinical implications of findings are discussed.

Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data

Abstract: In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same level as the storage device initiating the combined operation to allocate and store either the cast out or target data. A horizontal storage device having available space—i.e., an invalid or modified data element in a congruence class for the victim—stores either the target or the cast out data for subsequent access by an intervention. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.

Applying the Cox proportional hazards model for analysis of latency data with interval censoring.

Abstract: The latency time of an infectious disease is defined as the time from infection to disease onset. This paper applies the proportional hazards model to estimate the effect of covariates on latency when the time of disease onset is exact or right-censored but the time of infection is interval-censored. We use a Monte Carlo EM algorithm to estimate parameters of the joint distribution of infection times and latency times. At each EM iteration, exact infection times are multiply imputed from the density determined by the parameters of the infection and latency time distributions. The methodology is tested using a simulation study and is applied to data from a cohort of haemophiliacs with HIV disease.

Fairness scheme for a serial interface

Abstract: To maximize the throughput and minimize the latency associated with communications among devices on a single channel communications system, this invention provides a method and apparatus for a fairness based protocol that assures each device an equal opportunity to access the single channel communications system. The protocol forces a 'fairness' delay between each sequential transmission from a device, thereby allowing another device to gain access to the communications channel during this fairness delay period. In a preferred embodiment, the duration of each transmission is limited, thereby providing a maximum latency period for a device to gain access to the communications channel, and a minimum bandwidth allocation to the device. By providing a protocol having a guaranteed minimum bandwidth and maximum latency, a device in accordance with this invention need only contain the storage resources needed for the latency period.

A transformation for computational latency reduction in turbo-MAP decoding

Abstract: The SOVA and the log-MAP are commonly used in turbo decoding. In this paper, we propose to modify the sliding window MAP-algorithm to reduce the computational delay even further. We compare the simulation performance of this low latency log-MAP algorithm with the sliding window log-MAP. We also estimate the VLSI implementation complexities of the SOVA, the log-MAP and the proposed low latency log-MAP.

System and method for reducing latency in software modem for high-speed synchronous transmission

Abstract: An ADSL physical transmission layer (110) retrieves data to be transmitted from either a transmit data buffer (115), or a dummy cell buffer (130) in the case when no actual data is being transmitted to maintain a continuous data stream in an ADSL data link. The ADSL physical transmission layer (110) and an associated ATM protocol layer (120) are implemented as an interrupt service routine and delayed procedure call respectively in an ADSL software modem application. Because the ATM protocol layer (120) does not fill the transmit data buffer (115) with dummy cell data, it is simpler and faster. Moreover, latency is minimized, and overall system throughput enhanced since the maximum latency is independent of any operating system latency, and is no greater than the size of the cell stored in the dummy cell buffer (130). The invention has significant potential for performance and latency of computing systems pose engineering challenges in maintaining a continuous data link between a real time transceiver and a non-real time operating system.