Showing papers on "Latency (engineering) published in 2009"

Matchmaking for online games and other latency-sensitive P2P systems

Abstract: The latency between machines on the Internet can dramatically affect users' experience for many distributed applications. Particularly, in multiplayer online games, players seek to cluster themselves so that those in the same session have low latency to each other. A system that predicts latencies between machine pairs allows such matchmaking to consider many more machine pairs than can be probed in a scalable fashion while users are waiting. Using a far-reaching trace of latencies between players on over 3.5 million game consoles, we designed Htrae, a latency prediction system for game matchmaking scenarios. One novel feature of Htrae is its synthesis of geolocation with a network coordinate system. It uses geolocation to select reasonable initial network coordinates for new machines joining the system, allowing it to converge more quickly than standard network coordinate systems and produce substantially lower prediction error than state-of-the-art latency prediction systems. For instance, it produces 90th percentile errors less than half those of iPlane and Pyxida. Our design is general enough to make it a good fit for other latency-sensitive peer-to-peer applications besides game matchmaking.

Effects of tracking technology, latency, and spatial jitter on object movement

Abstract: We investigate the effects of input device latency and spatial jitter on 2D pointing tasks and 3D object movement tasks. First, we characterize jitter and latency in a 3D tracking device and an optical mouse used as a baseline comparison. We then present an experiment based on ISO 9241-9, which measures performance characteristics of pointing devices. We artificially introduce latency and jitter to the mouse and compared the results to the 3D tracker. Results indicate that latency has a much stronger effect on human performance than low amounts of spatial jitter. In a second study, we use a subset of conditions from the first to test latency and jitter on 3D object movement. The results indicate that large, uncharacterized jitter “spikes” significantly impact 3D performance.

Risk assessment in man and mouse

Abstract: Human and mouse subjects tried to anticipate at which of 2 locations a reward would appear. On a randomly scheduled fraction of the trials, it appeared with a short latency at one location; on the complementary fraction, it appeared after a longer latency at the other location. Subjects of both species accurately assessed the exogenous uncertainty (the probability of a short versus a long trial) and the endogenous uncertainty (from the scalar variability in their estimates of an elapsed duration) to compute the optimal target latency for a switch from the short- to the long-latency location. The optimal latency was arrived at so rapidly that there was no reliably discernible improvement over trials. Under these nonverbal conditions, humans and mice accurately assess risks and behave nearly optimally. That this capacity is well-developed in the mouse opens up the possibility of a genetic approach to the neurobiological mechanisms underlying risk assessment.

Determinants of the Establishment of Human Immunodeficiency Virus Type 1 Latency

Abstract: Recent research has emphasized the notion that human immunodeficiency virus type 1 (HIV-1) latency is controlled by a restrictive histone code at, or DNA methylation of, the integrated viral promoter (long terminal repeat [LTR]). The present concept of HIV-1 latency has essentially been patterned from the principles of cellular gene regulation. Here we introduce an experimental system that allows for the qualitative and quantitative kinetic study of latency establishment and maintenance at the population level. In this system, we find no evidence that HIV-1 latency establishment is the consequence of downregulation of initial active infection followed by the establishment of a restrictive histone code at the viral LTR. Latent infection was established following integration of the virus in the absence of viral gene expression (silent integration) and was a function of the NF-κB activation level in the host cell at the time of infection. In the absence of a role for epigenetic regulation, we demonstrate that transcriptional interference, a mechanism that has recently been suggested to add to the stabilization of HIV-1 latency, is the primary mechanism to govern latency maintenance. These findings provide direct experimental evidence that the high number of viral integration events (>90%) found in actively expressed genes of CD4 + memory T cells from highly active antiretroviral therapy-suppressed patients represent indeed latent infection events and that transcriptional interference may be the primary mechanism to control HIV-1 latency in vivo. HIV-1 latency may thus not be governed by the principles of cellular gene regulation, and therapeutic strategies to deplete the pool of latently HIV-1-infected cells should be reconsidered.

Prediction router: Yet another low latency on-chip router architecture

Abstract: Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce the communication latency, we propose a low-latency router architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration. In the prediction routers, incoming packets are transferred without waiting the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing the communication latency is the hit rates of prediction algorithms, which vary from the network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-latency routers that speculatively skip one or more pipeline stages use a bypass datapath for specific packet transfers (e.g., packets moving on the same dimension), our prediction router predictively forwards packets based on a prediction algorithm selected from several candidates in response to the network environments. In this paper, we analyze the prediction hit rates of six prediction algorithms on meshes, tori, and fat trees. Then we provide three case studies, each of which assumes different many-core architecture. We have implemented a prediction router for each case study by using a 65nm CMOS process, and evaluated them in terms of the prediction hit rate, zero load latency, hardware amount, and energy consumption. The results show that although the area and energy are increased by 6.4–15.9% and 8.0–9.5% respectively, up to 89.8% of the prediction hit rate is achieved in real applications, which provide favorable trade-offs between the modest hardware/energy overheads and the latency saving.

The tradeoff between spatial jitter and latency in pointing tasks

Abstract: Interactive computing systems frequently use pointing as an input modality, while also supporting other forms of input such as alphanumeric, voice, gesture, and force.We focus on pointing and investigate the effects of input device latency and spatial jitter on 2D pointing speed and accuracy. First, we characterize the latency and jitter of several common input devices. Then we present an experiment, based on ISO 9241-9, where we systematically explore combinations of latency and jitter on a desktop mouse to measure how these factors affect human performance. The results indicate that, while latency has a stronger effect on human performance compared to low amounts of spatial jitter, jitter dramatically increases the error rate, roughly inversely proportional to the target size.The findings can be used in the design of pointing devices for interactive systems, by providing a guideline for choosing parameters of spatial filtering to compensate for jitter, since stronger filtering typically also increases lag. We also describe target sizes at which error rates start to increase notably, as this is relevant for user interfaces where hand tremor or similar factors play a major role.

Tolerating latency in replicated state machines through client speculation

Abstract: Replicated state machines are an important and widely-studied methodology for tolerating a wide range of faults. Unfortunately, while replicas should be distributed geographically for maximum fault tolerance, current replicated state machine protocols tend to magnify the effects of high network latencies caused by geographic distribution. In this paper, we examine how to use speculative execution at the clients of a replicated service to reduce the impact of network and protocol latency. We first give design principles for using client speculation with replicated services, such as generating early replies and prioritizing throughput over latency. We then describe a mechanism that allows speculative clients to make new requests through replica-resolved speculation and predicated writes. We implement a detailed case study that applies this approach to a standard Byzantine fault tolerant protocol (PBFT) for replicated NFS and counter services. Client speculation trades in 18% maximum throughput to decrease the effective latency under light workloads, letting us speed up run time on single-client micro-benchmarks 1.08-19× when the client is co-located with the primary. On a macro-benchmark, reduced latency gives the client a speedup of up to 5×.

Motivating future interconnects: a differential measurement analysis of PCI latency

Abstract: Local interconnect architectures are at a cusp in which advances in throughput have come at the expense of power and latency. Moreover, physical limits imposed on dissipation and packaging mean that further advances will require a new approach to interconnect design. Although latency in networks has been the focus of the High-Performance Computing architect and of concern across the computer community, we illustrate how an evolution in the common PCI interconnect architecture has worsened latency by a factor of between 3 and 25 over earlier incarnations.

Relating Scene-Motion Thresholds to Latency Thresholds for Head-Mounted Displays

Abstract: As users of head-tracked head-mounted display systems move their heads, latency causes unnatural scene motion. We 1) analyzed scene motion due to latency and head motion, 2) developed a mathematical model relating latency, head motion, scene motion, and perception thresholds, 3) developed procedures to determine perceptual thresholds of scene-velocity and latency without the need for a head-mounted display or a low-latency system, and 4), for six subjects under a specific set of conditions, we measured scene-velocity and latency thresholds and compared the relationship between these thresholds. Resulting PSEs (min 10 ms) and JNDs (min 3 ms) of latency thresholds are in a similar range reported by Ellis and Adelstein. The results are a step toward enabling scientists and engineers to determine latency requirements before building immersive virtual environments using head-mounted display systems.

An improved approximation algorithm for data aggregation in multi-hop wireless sensor networks

Abstract: Data aggregation is an efficient primitive in wireless sensor network (WSN) applications. This paper focuses on data aggregation scheduling problem to minimize the latency. We propose an efficient distributed method that produces a collision-free schedule for data aggregation in WSNs. We prove that the latency of the aggregation schedule generated by our algorithm is at most 16R+Δ--14 time-slots. Here R is the network radius and Δ is the maximum node degree in the communication graph of the original network. Our method significantly improves the previously known best data aggregation algorithm [3], that has a latency bound of 24D+6Δ+16 time-slots, where D is the network diameter (Note that D can be as large as 2R). We conduct extensive simulations to study the practical performances of our proposed data aggregation method. Our simulation results corroborate our theoretical results and show that our algorithms perform better in practice.We prove that the overall lower-bound of latency of data aggregation under any interference model is max{log n, R} where n is the network size. We provide an example to show that the lower-bound is (approximately) tight under protocol interference model when rI=r, where rI is the interference range and r is the transmission range. We also derive the lower-bound of latency under protocol interference model when r

Dynamics of latent voters

Abstract: We study the effect of latency on binary-choice opinion formation models. Latency is introduced into the models as an additional dynamic rule: after a voter changes its opinion, it enters a waiting period of stochastic length where no further changes take place. We first focus on the voter model and show that as a result of introducing latency, the average magnetization is not conserved, and the system is driven toward zero magnetization, independently of initial conditions. The model is studied analytically in the mean-field case and by simulations in one dimension. We also address the behavior of the majority-rule model with added latency, and show that the competition between imitation and latency leads to a rich phenomenology.

Random linear network coding for time division duplexing

Abstract: A new random linear network coding scheme for reliable communications for time division duplexing channels is proposed. The setup assumes a packet erasure channel and that nodes cannot transmit and receive information simultaneously. The sender transmits coded data packets back-to-back before stopping to wait for the receiver to acknowledge (ACK) the number of degrees of freedom, if any, that are required to decode correctly the information. Provided herein is an analysis of this problem to show that there is an optimal number of coded data packets, in terms of mean completion time, to be sent before stopping to listen. This number depends on the latency, probabilities of packet erasure and ACK erasure, and the number of degrees of freedom that the receiver requires to decode the data. This scheme is optimal in terms of the mean time to complete the transmission of a fixed number of data packets. It is shown that its performance is very close to that of a full-duplex system, while transmitting a different number of coded packets can cause large degradation in performance, especially if latency is high. Also described herein is the throughput performance of the novel system and technique along with a comparison to existing half-duplex Go-back-N and Selective Repeat ARQ schemes. Numerical results, obtained for different latencies, show that the novel system and technique described herein has similar performance to the Selective Repeat in most cases and considerable performance gain when latency and packet error probability is high.

Process variation aware thread mapping for chip multiprocessors

Abstract: With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions. With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiprocessors (CMPs) for example, it is possible that identically-designed processor cores on the chip have non-identical peak frequencies and power consumptions. To cope with such a design, each processor can be assumed to run at the frequency of the slowest processor, resulting in wasted computational capability. This paper considers an alternate approach and proposes an algorithm that intelligently maps (and remaps) computations onto available processors so that each processor runs at its peak frequency. In other words, by dynamically changing the thread-to-processor mapping at runtime, our approach allows each processor to maximize its performance, rather than simply using chip-wide lowest frequency amongst all cores and highest cache latency. Experimental evidence shows that, as compared to a process variation agnostic thread mapping strategy, our proposed scheme achieves as much as 29% improvement in overall execution latency, average improvement being 13% over the benchmarks tested. We also demonstrate in this paper that our savings are consistent across different processor counts, latency maps, and latency distributions.

QoS-Aware Wavelength Assignment With BER and Latency Constraints for All-Optical Networks

Abstract: Physical impairments originating from optical fiber components and intermediate switching nodes can be the dominant reason calls are blocked in wide-area all-optical wavelength division multiplexing (WDM) networks. When a centralized network controller is used, estimating the impact of the physical impairments on the quality of a lightpath before provisioning it can cause a significant delay. In this paper, quality of service aware wavelength assignment algorithms are proposed that consider both bit-error rate (BER) and latency constraints. A novel wavelength assignment technique called wavelength ordering is shown via simulation to reduce the call blocking probability resulting from both physical impairments and excessive processing delay caused by channel BER estimation.

Establishing optimal latency in streaming data applications that use data packets

Abstract: Embodiments for an apparatus and method are provided that can build latency in streaming applications that use data packets In an embodiment, a system has an under-run forecasting mechanism, a statistics monitoring mechanism, and a playback queuing mechanism The under-run forecasting mechanism determines an estimate of when a supply of data packets to convert will be exhausted The statistics monitoring mechanism measures the arrival fluctuations of the supply of data packets The playback queuing mechanism can build the latency

Method and system for improving serial port memory communication latency and reliability

Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Visual evoked responses to pattern-reversal stimulation in patients with amblyopia and/or defective binocular functions.

Abstract: The visual evoked responses to monocular and binocular pattern-reversal stimulation were recorded in ten normal subjects and in ten cases with amblyopia and/or defective binocular functions. Seven of the ten patients showed a considerable amplitude asymmetry to monocular stimulation or lack of normal increase of amplitude to binocular stimulation. Two patients displayed prolonged latency on stimulation of the amblyopic eye.

Latency counter, semiconductor memory device including the same, and data processing system

Abstract: A latency counter includes: a frequency-dividing circuit that generates a plurality of divided clocks LCLKE and LCLKO of which the phases differ each other based on an internal clock LCLK; and frequency-divided counter circuits each of which counts a latency of an internal command based on the corresponding divided clocks LCLKE and LCLKO. Thus, the counting of the latency is performed based not on the internal clock LCLK itself but on the divided clocks LCLKE and LCLKO obtained by frequency-dividing the internal clock LCLK. Thus, even when a frequency of the internal clock LCLK is high, an operation margin can be sufficiently secured.

Estimating latencies for query optimization in distributed stream processing

Abstract: A “Query Optimizer” provides a cost estimation metric referred to as “Maximum Accumulated Overload” (MAO). MAO is approximately equivalent to maximum system latency in a data stream management system (DSMS). Consequently, MAO is directly relevant for use in optimizing latencies in real-time streaming applications running multiple continuous queries (CQs) over high data-rate event sources. In various embodiments, the Query Optimizer computes MAO given knowledge of original operator statistics, including “operator selectivity” and “cycles/event” in combination with an expected event arrival workload. Beyond use in query optimization to minimize worst-case latency, MAO is useful for addressing problems including admission control, system provisioning, user latency reporting, operator placements (in a multi-node environment), etc. In addition, MAO, as a surrogate for worst-case latency, is generally applicable beyond streaming systems, to any queue-based workflow system with control over the scheduling strategy.

An Image-Warping Architecture for VR: Low Latency versus Image Quality

Abstract: Designing low end-to-end latency system architectures for virtual reality is still an open and challenging problem. We describe the design, implementation and evaluation of a client-server depth-image warping architecture that updates and displays the scene graph at the refresh rate of the display. Our approach works for scenes consisting of dynamic and interactive objects. The end-to-end latency is minimized as well as smooth object motion generated. However, this comes at the expense of image quality inherent to warping techniques. We evaluate the architecture and its design trade-offs by comparing latency and image quality to a conventional rendering system. Our experience with the system confirms that the approach facilitates common interaction tasks such as navigation and object manipulation.

Measuring Latency for Video Surveillance Systems

Abstract: The increased flexibility and other benefits offered by IP network cameras makes them a common choice for installation in new and expanded surveillance networks. One commonly quoted limitation of IP cameras is their high latency when compared to their analogue counterparts. This causes some reluctance to install or upgrade to digital cameras, and is slowing the adoption of live, intelligent analysis techniques in video surveillance systems. This paper presents methods for measurement of the latency in systems based upon digital IP or analogue cameras. These methods are camera-agnostic and require no specialised hardware. We use these methods to compare a variety of camera models. The results demonstrate that whilst analogue cameras do have a lower latency, most IP cameras are within acceptable tolerances. The source of the latency within an IP camera is also analysed, with prospects for improvement identified.

Zero-latency network on chip (noc)

Abstract: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications

Best of both worlds: A bus enhanced NoC (BENoC)

Abstract: While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficient for multicast operations. Consequently, although NoCs outperform busses in terms of scalability, they may not facilitate all the needs of future SoCs. In this paper, the benefit of adding a global, low latency, low power shared bus as an integral part of the NoC architecture is explored. The Bus-enhanced NoC (BENoC) is equipped with a specialized bus that has low and predictable latency and performs broadcast and multicast. We introduce and analyze MetaBus, a custom bus optimized for such low-latency low power and multicast operations. We demonstrate its potential benefits using an analytical comparison of latency and energy consumption of a BENoC based on MetaBus versus a standard NoC. Then, simulation is used to evaluate BENoC in a dynamic non-uniform cache access (DNUCA) multiprocessor system.

System and Method for Latency Reduction for Automatic Speech Recognition Using Partial Multi-Pass Results

Abstract: A system and method is provided for reducing latency for automatic speech recognition. In one embodiment, intermediate results produced by multiple search passes are used to update a display of transcribed text.

A Resource Optimized Remote-Memory-Access Architecture for Low-latency Communication

Abstract: This paper introduces a new highly optimized architecture for remote memory access (RMA). RMA, using put and get operations, is a one-sided communication function which amongst others is important in current and upcoming Partitioned Global Address Space (PGAS) systems. In this work, a virtualized hardware unit is described which is resource optimized, exhibits high overlap, processor offload and very good latency characteristics. To start an RMA operation a single HyperTransport packet caused by one CPU instruction is sufficient, thus reducing latency to an absolute minimum. In addition to the basic architecture an implementation in FPGA technology is presented together with an evaluation of the target ASIC-implementation. The current system can sustain more than 4.9 million transactions per second on the FPGA and exhibits an end-to-end latency of 1.2 μs for an 8-byte put operation. Both values are limited by the FPGA technology used for the prototype implementation. An estimation of the performance reachable on ASIC technology suggests that application to application latencies of less than 500 ns are feasible.

A multi-hop reservation method for end-to-end latency performance improvement in asynchronous MAC-based wireless sensor networks

Abstract: Duty cycling is a common mechanism for achieving energy efficiency in WSNs. Over the past several years a number of researchers have proposed low-power duty-cycle MAC protocols, but the tradeoff between energy efficiency and latency has been remained a challenging issue. We propose the Express-MAC protocol (EX-MAC) which can guarantee the requirement of the end-to-end transmission latency while conserving energy in a wireless sensor network using asynchronous duty cycling. To achieve low latency operation, EX-MAC employs a wakeup time reservation that utilizes a short preamble scheme to reduce end-to-end latency and to minimize energy consumption. Also, EX-MAC supports multi-hop applications through a cross-layering API, and it provides convergecast packets with unidirectional interfaces to optimize performance and to support reconfiguration routing. In this paper, we first introduce WSNs and the problems in existing MAC protocols. Then we propose the EXMAC protocol for low end-to-end latency and power efficiency in WSNs. From simulation results, it is proven that EX-MAC is able to adjust its wakeup time reservation for convergecast traffic and to guarantee the requirement of endto- end latency.

Tri-Message: A Lightweight Time Synchronization Protocol for High Latency and Resource-Constrained Networks

Abstract: Existing terrestrial synchronization protocols including RBS, FTSP, TPSN, LTS and TSHL have already achieved high precision in radio networks, but none of them perform well in high latency networks like acoustic sensor networks. In this paper, we present Tri-Message: a lightweight time synchronization protocol for high latency and resource-constrained networks. As its name suggests, only three message exchanges are required in one synchronization process. Meanwhile, Tri-Message utilizes very simple mathematical operations to calculate the clock skew and offset. Specially, Tri-Message is feasible for many extremely long latency applications such as space exploration because it has an increasing synchronization precision with the increasement of distance.