Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.

Minimum-latency aggregation scheduling in wireless sensor network

Abstract: Data aggregation is an essential yet time-consuming task in wireless sensor networks. This paper studies the well-known minimum-latency aggregation schedule problem and proposes an energy-efficient distributed scheduling algorithm named Clu-DDAS based on a novel cluster-based aggregation tree. Our approach differs from all the previous schemes where connected dominating sets or maximal independent sets are employed. This paper proves that Clu-DDAS has a latency bound of $$4R'+2 \varDelta -2$$4R?+2Δ-2, where $$\varDelta $$Δ is the maximum degree and $$R'$$R? is the inferior network radius which is smaller than the network radius $$R$$R. Our experiments show that Clu-DDAS has an approximate latency upper bound of $$4R'+1.085 \varDelta -2$$4R?+1.085Δ-2 with increased $$\varDelta $$Δ. Clu-DDAS has comparable latency as the previously best centralized algorithm, E-PAS, but consumes 78 % less energy as shown by the simulation results. Clu-DDAS outperforms the previously best distributed algorithm, DAS, whose latency bound is $$16R'+\varDelta -14$$16R?+Δ-14 on both latency and energy consumption. On average, Clu-DDAS transmits 67 % fewer total messages than DAS. The paper also proposes an adaptive strategy for updating the schedule to accommodate dynamic network topology.

A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors

Abstract: The Chameleon CS2112 chip is the industry's first reconfigurable communication processor To attain high performance, the reconfiguration latency must be effectively tolerated in such a processor In this paper, we present a compiler directed approach to hiding the configuration loading latency We integrate multithreading, instruction scheduling, register allocation, and prefetching techniques to tolerate the configuration loading latency Furthermore, loading configuration is overlapped with communication to further enhance performance By running some kernel programs on a cycle-accurate simulator, we showed that the chip performance is significantly improved by leveraging such compiler and multithreading techniques

Direct measurement of the system latency of gaze-contingent displays

Abstract: Gaze-contingent displays combine a display device with an eyetracking system to rapidly update an image on the basis of the measured eye position. All such systems have a delay, the system latency, between a change in gaze location and the related change in the display. The system latency is the result of the delays contributed by the eyetracker, the display computer, and the display, and it is affected by the properties of each component, which may include variability. We present a direct, simple, and low-cost method to measure the system latency. The technique uses a device to briefly blind the eyetracker system (e.g., for video-based eyetrackers, a device with infrared light-emitting diodes (LED)), creating an eyetracker event that triggers a change to the display monitor. The time between these two events, as captured by a relatively low-cost consumer camera with high-speed video capability (1,000 Hz), is an accurate measurement of the system latency. With multiple measurements, the distribution of system latencies can be characterized. The same approach can be used to synchronize the eye position time series and a video recording of the visual stimuli that would be displayed in a particular gaze-contingent experiment. We present system latency assessments for several popular types of displays and discuss what values are acceptable for different applications, as well as how system latencies might be improved.

Network page latency reduction using gamma distribution

Abstract: Disclosed are various embodiments of a system, method and computer readable medium for network page latency reduction. In one embodiment, among others, a system comprises a processor circuit and a memory associated with the processor circuit. The system further comprises a distribution estimator configured to estimate a distribution corresponding to latency data regarding a plurality of instances of a network page. The system further comprises an attribute comparator configured to identify an attribute associated with a subset of the instances of a network page. The subset of the instances corresponds to a latency data substantially represented by a tail of the distribution. Additionally, the system comprises a recommendation generator configured to generate a modification recommendation for the subset of the instances of the network page.