Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.

Maintenance of gammaherpesvirus latency requires viral cyclin in the absence of B lymphocytes.

Abstract: Gammaherpesviruses establish a life-long chronic infection that is tightly controlled by the host immune response. We previously demonstrated that viruses lacking the gammaherpesvirus 68 (gammaHV68) viral cyclin (v-cyclin) exhibited a severe defect in reactivation from latency and persistent replication. In this analysis of chronic infection, we demonstrate that the v-cyclin is required for gammaHV68-associated mortality in B-cell-deficient mice. Furthermore, we identify the v-cyclin as the first gene product required for maintenance of gammaherpesvirus latency in vivo in the absence of B lymphocytes. While the v-cyclin was necessary for maintenance of latency in the absence of B cells, maintenance of v-cyclin-deficient viruses was equivalent to that of wild-type gammaHV68 in the presence of B cells. These results support a model in which maintenance of chronic gammaHV68 infection requires v-cyclin-dependent reactivation and reseeding of non-B-cell latency reservoirs in the absence of B cells and raise the possibility that B cells represent a long-lived latency reservoir maintained independently of reactivation. These results highlight distinct mechanisms for the maintenance of chronic infection in immunocompetent and B-cell-deficient mice and suggest that the different latency reservoirs have distinct gene requirements for the maintenance of latency.

Adaptive packet routing

Abstract: A method of determining the latency of a route in a packet-switched network, a packet switch for use in such a method and network and a packet-switched network are disclosed. Preferably, each switch maintains a routing table that records the latency of the routes accessible by that switch. Each switch also preferably has a GPS-based universal time clock which it employs to time the transmission and arrival of identifiable timing packets, these times being used to compute route latency and to up-date the routing tables. In one example ( FIG. 1 ) a packet-switched network has a plurality of switches (S 1 -S 6 ) interconnected by links or trunks (T 1 -T 7 ). A local GPS-base clock (GPS CLK) is connected to each switch (S 1 -S 6 ) to enable the accurate timing of transmission and reception of identifiable timing packets in accordance with a system-wide universal timing standard.

DARC: dynamic analysis of root causes of latency distributions

Abstract: OSprof is a versatile, portable, and efficient profiling methodology based on the analysis of latency distributions. Although OSprof has offers several unique benefits and has been used to uncover several interesting performance problems, the latency distributions that it provides must be analyzed manually. These latency distributions are presented as histograms and contain distinct groups of data, called peaks, that characterize the overall behavior of the running code. By automating the analysis process, we make it easier to take advantage of OSprof's unique features.We have developed the Dynamic Analysis of Root Causes system (DARC), which finds root cause paths in a running program's call-graph using runtime latency analysis. A root cause path is a call-path that starts at a given function and includes the largest latency contributors to a given peak. These paths are the main causes for the high-level behavior that is represented as a peak in an OSprof histogram. DARC performs PID and call-path filtering to reduce overheads and perturbations, and can handle recursive and indirect calls. DARC can analyze preemptive behavior and asynchronous call-paths, and can also resume its analysis from a previous state, which is useful when analyzing short-running programs or specific phases of a program's execution.We present DARC and show its usefulness by analyzing behaviors that were observed in several interesting scenarios. We also show that DARC has negligible elapsed time overheads for normal use cases.

Improving phase change memory performance with data content aware access

Abstract: Phase change memory (PCM) is a scalable non-volatile memory technology that has low access latency (like DRAM) and high capacity (like Flash). Writing to PCM incurs significantly higher latency and energy penalties compared to reading its content. A prominent characteristic of PCM’s write operation is that its latency and energy are sensitive to the data to be written as well as the content that is overwritten. We observe that overwriting unknown memory content can incur significantly higher latency and energy compared to overwriting known all-zeros or all-ones content. This is because all-zeros or all-ones content is overwritten by programming the PCM cells only in one direction, i.e., using either SET or RESET operations, not both. In this paper, we propose data content aware PCM writes (DATACON), a new mechanism that reduces the latency and energy of PCM writes by redirecting these requests to overwrite memory locations containing all-zeros or all-ones. DATACON operates in three steps. First, it estimates how much a PCM write access would benefit from overwriting known content (e.g., all-zeros, or all-ones) by comprehensively considering the number of set bits in the data to be written, and the energy-latency trade-offs for SET and RESET operations in PCM. Second, it translates the write address to a physical address within memory that contains the best type of content to overwrite, and records this translation in a table for future accesses. We exploit data access locality in work- loads to minimize the address translation overhead. Third, it re-initializes unused memory locations with known all- zeros or all-ones content in a manner that does not interfere with regular read and write accesses. DATACON overwrites unknown content only when it is absolutely necessary to do so. We evaluate DATACON with workloads from state- of-the-art machine learning applications, SPEC CPU2017, and NAS Parallel Benchmarks. Results demonstrate that DATACON improves the effective access latency by 31%, overall system performance by 27%, and total memory system energy consumption by 43% compared to the best of performance-oriented state-of-the-art techniques.