Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.

Method and system for mapping virtual connections to asymmetric digital subscriber line latency paths

Abstract: A method and system for mapping virtual connections to asymmetric digital subscriber line (“ADSL”) latency paths. A request for virtual connection from a transport network (e.g., Asynchronous Transport Mode, Frame Relay, etc.) with a desired service category (e.g., quality-of-service) and a desired latency is mapped to an ADSL device latency interface by checking a latency mapping policy. This mapping provides a virtual connection with a desired service category and a desired latency over ADSL links. The latency mapping includes an embedded service category mapping from a transport network to latency paths at an ADSL transmission convergence sub-layer allowing differential services to be provided for user data based on a desired service category. The latency mapping mechanism may help provide use of end-to-end service categories such as quality-of-service categories, over real-time ADSL links.

On Checkpoint Latency

Abstract: Checkpointing and rollback is a technique to minimize the loss of computation in the presence of failures. Two metrics can be used to characterize a checkpointing scheme: (i) checkpoint overhead (increase in the execution time of the appliction because of a checkpoint), and (ii) checkpoint latency (duration of time required to save the checkpoint). The contributions of this report are as follows: 1. The report evaluates the expression for average overhead of the recovery scheme as a function of checkpoint latency and overhead. 2. A mechanism that attempts to reduce checkpoint overhead usually causes an increase in the checkpoint latency. A decrease in checkpoint overhead can result in an increase or a decrease in the average overhead, depending on whether the latency is increased "too much" or not. This report determines a function g of checkpoint overhead C such that checkpoint latency should be less that g(C) to achieve a decrease in the average overhead. 3. For equi-distant checkpoints, the optimal checkpoint interval is shown to be independent of the checkpoint latency (L).

Differential latency testing : A more sensitive test for radial tunnel syndrome

Abstract: A modification of the standard electrodiagnostic test was developed in an effort to provide a more sensitive electrodiagnostic evaluation in radial tunnel syndrome. Radial motor nerve latency recordings were obtained in 3 different forearm positions: neutral, passive supination, and passive pronation. The maximal difference in these recordings, the differential latency, in 25 patients with radial tunnel syndrome of greater than 6 months duration (test group) was compared with those in 25 asymptomatic volunteers (control group). Differential latency recordings were obtained in all patients in the test group before and after surgery. Radial nerves that were compressed demonstrated a significantly greater differential latency (0.44±0.12 ms) versus controls (0.12±0.008 ms). Following radial nerve decompression, differential motor latencies in the test group decreased below control values, demonstrating a resolution of the provoked electrical response with a postoperative differential latency of 0.07±0.05 ms. Our results demonstrate the differential motor latency of the radial nerve to be a sensitive electrodiagnostic tool in patients with radial tunnel syndrome. A differential latency of ≥0.30 ms was considered indicative of radial tunnel syndrome.

SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model

Abstract: In this work, we propose SVR-NoC, a learning-based support vector regression (SVR) model for evaluating Network-on-Chip (NoC) latency performance. Different from the state-of-the-art NoC analytical model, which uses classical queuing theory to directly compute the average channel waiting time, the proposed SVR-NoC model performs NoC latency analysis based on learning the typical training data. More specifically, we develop a systematic machine-learning framework that uses the kernel-based support vector regression method to predict the channel average waiting time and the traffic flow latency. Experimental results show that SVR-NoC can predict the average packet latency accurately while achieving about 120X speed-up over simulation-based evaluation methods.

A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures

Abstract: In this paper, we propose SVR-NoC, a network-on-chip (NoC) latency model using support vector regression (SVR). More specifically, based on the application communication information and the NoC routing algorithm, the channel and source queue waiting times are first estimated using an analytical queuing model with two equivalent queues. To improve the prediction accuracy, the queuing theory-based delay estimations are included as features in the learning process. We then propose a learning framework that relies on SVR to collect training data and predict the traffic flow latency. The proposed learning methods can be used to analyze various traffic scenarios for the target NoC platform. Experimental results on both synthetic and real-application traffic demonstrate on average less than 12% prediction error in network saturation load, as well as more than $100\times $ speedup compared to cycle-accurate simulations can be achieved.