Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.

Regions of the Varicella-Zoster Virus Open Reading Frame 63 Latency-Associated Protein Important for Replication In Vitro Are Also Critical for Efficient Establishment of Latency

Abstract: Varicella-zoster virus (VZV) open reading frame 63 (ORF63) is one of the most abundant transcripts expressed during VZV latency in humans, and ORF63 protein has been detected in human ganglia by several laboratories. Deletion of over 90% of the ORF63 gene showed that the protein is required for efficient establishment of latency in rodents. We have constructed viruses with a series of mutations in ORF63. While prior experiments showed that transfection of cells with a plasmid expressing ORF63 but lacking the putative nuclear localization signal of the protein resulted in increased expression of the protein in the cytoplasm, we found that ORF63 protein remained in the nucleus in cells infected with a VZV ORF63 nuclear localization signal deletion mutant. This mutant was not impaired for growth in cell culture or for latency in rodents. Replacement of five serine or threonine phosphorylation sites in ORF63 with alanines resulted in a virus that was impaired for replication in vitro and for latency. A series of ORF63 carboxy-terminal mutants showed that the last 70 amino acids do not affect replication in vitro or latency in rodents; however, the last 108 amino acids are important for replication and latency. Thus, regions of ORF63 that are important for replication in vitro are also required for efficient establishment of latency.

Latency counter, semiconductor memory device including the same, and data processing system

Abstract: A latency counter includes: a frequency-dividing circuit that generates a plurality of divided clocks LCLKE and LCLKO of which the phases differ each other based on an internal clock LCLK; and frequency-divided counter circuits each of which counts a latency of an internal command based on the corresponding divided clocks LCLKE and LCLKO. Thus, the counting of the latency is performed based not on the internal clock LCLK itself but on the divided clocks LCLKE and LCLKO obtained by frequency-dividing the internal clock LCLK. Thus, even when a frequency of the internal clock LCLK is high, an operation margin can be sufficiently secured.

Time-based correlation of non-translative network segments

Abstract: Methods and systems for correlating network traffic between non-translative network systems are provided. Generally, time-based offset data, or transmission latency, is first determined between devices in non-translative network segments by injecting, with a time stamp, a known network pattern at a first end of the network topology. Traces are then recorded, with time stamps, of the network traffic over one or more nodes throughout the non-translative network. The generate network traffic is then compared to the traced network traffic in a best fit to thereby determine the time latency in traffic throughout the network. Later, when it is desired to determine causality of network activity between non-translative network segments, the determined latency between different network devices can be compared to traced patterns of network traffic to determine the origin of a network operation that created an observed event.

Addressing End-to-End Memory Access Latency in NoC-Based Multicores

Abstract: To achieve high performance in emerging multicores, it is crucial to reduce the number of memory accesses that suffer from very high latencies. However, this should be done with care as improving latency of an access can worsen the latency of another as a result of resource sharing. Therefore, the goal should be to balance latencies of memory accesses issued by an application in an execution phase, while ensuring a low average latency value. Targeting Network-on-Chip (NoC) based multicores, we propose two network prioritization schemes that can cooperatively improve performance by reducing end-to-end memory access latencies. Our first scheme prioritizes memory response messages such that, in a given period of time, messages of an application that experience higher latencies than the average message latency for that application are expedited and a more uniform memory latency pattern is achieved. Our second scheme prioritizes the request messages that are destined for idle memory banks over others, with the goal of improving bank utilization and preventing long queues from being built in front of the memory banks. These two network prioritization-based optimizations together lead to uniform memory access latencies with a low average value. Our experiments with a 4x8 mesh network-based multicore show that, when applied together, our schemes can achieve 15%, 10% and 13% performance improvement on memory intensive, memory non-intensive, and mixed multiprogrammed workloads, respectively.