Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.

Variation of sympathetic reflex latency in man.

Abstract: Microelectrode recordings of muscle nerve sympathetic activity (MSA) in man have shown a reflex relationship between heart beat and corresponding sympathetic burst, the latency of which is stable at rest and independent of heart rate. In peroneal nerve recordings in 35 healthy subjects this latency was reduced during the Valsalva manoeuvre by 120 ms (mean; range 40–245 ms; P < 0.001) from a mean value at rest of 1300 ms. Slow deep breathing and simulated diving shortened the latency by 60 (P < 0.001) and 80 ms (P < 0.05), respectively. When intrinsic heart rate was induced by i.v. administration of atropine and propranolol, the latency was increased by 70 ms (P < 0.001). A number of other manoeuvres affecting the outflow of MSA did not change the latency. It is suggested that the findings indicate the existence of more than one central pathway involved in the baroreflex regulation of MSA. Alternatively, altered central processing time may follow influence from other receptors in different manoeuvres.

Naming latencies as evidence for two modes of lexical retrieval

Abstract: Data are reported for response latencies to naming pictures of objects which show a systematic relationship between naming latency and two measures of item difficulty. Of primary interest was a reanalysis of full latency distributions on a picture-by-picture basis to explore the possibility that overall mean latencies could in actuality be composed of multiple independent latency populations. Results are discussed in terms of “automatic” versus “voluntary search” modes of word retrieval.

Parallel Chains: Improving Throughput and Latency of Blockchain Protocols via Parallel Composition.

Abstract: Two of the most significant challenges in the design of blockchain protocols is increasing their transaction processing throughput and minimising latency in terms of transaction settlement. In this work we put forth for the first time a formal execution model that enables to express transaction throughput while supporting formal security arguments regarding safety and liveness. We then introduce parallel-chains, a simple yet powerful non-black-box composition technique for blockchain protocols. We showcase our technique by providing two parallel-chains protocol variants, one for the PoS and one for PoW setting, that exhibit optimal throughput under adaptive fail-stop corruptions while they retain their resiliency in the face of Byzantine adversity assuming honest majority of stake or computational power, respectively. We also apply our parallel-chains composition method to improve settlement latency; combining parallel composition with a novel transaction weighing mechanism we show that it is possible to scale down the time required for a transaction to settle by any given constant while maintaining the same level of security.

A Low-Latency and Memory-Efficient On-chip Network

Abstract: Using multiple SDRAMs in MPSoCs and NoCs to increase memory parallelism is very common nowadays. In-order delivery, resource utilization, and latency are the most critical issues in such architectures. In this paper, we present a novel network interface architecture to cope with these issues efficiently. The proposed network interface exploits a resourceful reordering mechanism to handle the in-order delivery and to increase the resource utilization. A brilliant memory controller is efficiently integrated into this network interface to improve the memory utilization and reduce both memory and network latencies. In addition, to bring compatibility with existing IP cores the proposed network interface utilizes AXI transaction based protocol. Experimental results with synthetic test cases demonstrate that the proposed architecture gives significant improvements in average network latency (12%), average memory access latency (19%), and average memory utilization (22%).