Topic
Latency (engineering)
About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.
Papers published on a yearly basis
Papers
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TL;DR: The relationship of viral latency to gene-silencing mechanisms is reviewed, and it is shown that at least two gene- silencing mechanisms are used against the human immuno-deficiency virus.
Abstract: One of the cellular defenses against virus infection is the silencing of viral gene expression. There is evidence that at least two gene-silencing mechanisms are used against the human immuno-deficiency virus (HIV). Paradoxically, this cellular defense mechanism contributes to viral latency and persistence, and we review here the relationship of viral latency to gene-silencing mechanisms.
37 citations
01 Jan 1995
TL;DR: This chapter contains sections titled: Why Consider Petaflops Now?
Abstract: This chapter contains sections titled: Why Consider Petaflops Now?, Role of a Petaflops Computer, Side-effect Products, Impact of Exotic Technologies, Performance Versus Efficiency, Programming Paradigms, U.S. Capabilities in Memory Fabrication, Special Widgets, Where to Invest, A Range of Architectures, Far-side Architectures, Latency Hiding Techniques, Long versus Short Latency Machines, SIA Predictions, I/O Scaling
37 citations
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01 Apr 2017TL;DR: This work addresses the challenge of allowing simultaneous and predictable accesses to shared data on multicore systems by augmenting the classic modify-share-invalid protocol with transient coherence states, and minimal architectural changes, to derive worst-case latency bounds on predictable MSI (PMSI) protocol.
Abstract: This work addresses the challenge of allowing simultaneous and predictable accesses to shared data on multicore systems. We propose a predictable cache coherence protocol, which mandates the use of certain invariants to ensure predictability. In particular, we enforce these invariants by augmenting the classic modify-share-invalid (MSI) protocol with transient coherence states, and minimal architectural changes. This allows us to derive worst-case latency bounds on predictable MSI (PMSI) protocol. Our analysis shows that while the arbitration latency scales linearly, the coherence latency scales quadratically with the number of cores, which emphasizes that importance of accounting for cache coherence effects on latency bounds. We implement PMSI in gem5, and execute SPLASH-2 and synthetic workloads. Results show that our approach is always within the analytical worst-case latency bounds, and that PMSI improves averagecase performance by up to 4 over the next best predictable alternative. PMSI has average slowdowns of 1.45 and 1.46 compared to MSI and MESI protocols, respectively.
37 citations
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TL;DR: It is indicated that a varying latency is associated with greater experience of SS among HMD users than constant latency, and that added constant latency on its own does not appear to be associated with the experience of higher levels of SS in an HMD.
37 citations
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14 Oct 2009TL;DR: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameters governing latency penalty.
Abstract: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications
37 citations