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Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.


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TL;DR: In this paper, an analytical study of the latency performance of redundant requests is presented, with the primary goals of characterizing under what scenarios sending redundant requests will help and under what scenario they will not help.
Abstract: Several systems possess the flexibility to serve requests in more than one way. For instance, a distributed storage system storing multiple replicas of the data can serve a request from any of the multiple servers that store the requested data, or a computational task may be performed in a compute-cluster by any one of multiple processors. In such systems, the latency of serving the requests may potentially be reduced by sending "redundant requests": a request may be sent to more servers than needed, and it is deemed served when the requisite number of servers complete service. Such a mechanism trades off the possibility of faster execution of at least one copy of the request with the increase in the delay due to an increased load on the system. Due to this tradeoff, it is unclear when redundant requests may actually help. Several recent works empirically evaluate the latency performance of redundant requests in diverse settings. This work aims at an analytical study of the latency performance of redundant requests, with the primary goals of characterizing under what scenarios sending redundant requests will help (and under what scenarios they will not help), as well as designing optimal redundant-requesting policies. We first present a model that captures the key features of such systems. We show that when service times are i.i.d. memoryless or "heavier", and when the additional copies of already-completed jobs can be removed instantly, redundant requests reduce the average latency. On the other hand, when service times are "lighter" or when service times are memoryless and removal of jobs is not instantaneous, then not having any redundancy in the requests is optimal under high loads. Our results hold for arbitrary arrival processes.

118 citations

Journal ArticleDOI
17 Jul 2018-AIDS
TL;DR: PD-1 contributes to the establishment and maintenance of HIV latency and should be explored as a target, in combination with other immune checkpoint molecules, to reverse latency.
Abstract: Objective:In HIV-infected individuals on antiretroviral therapy (ART), latent HIV is enriched in CD4+ T cells expressing immune checkpoint molecules, in particular programmed cell death-1 (PD-1). We therefore assessed the effect of blocking PD-1 on latency, both in vitro and in vivo.Methods:HIV late

118 citations

Proceedings ArticleDOI
23 Feb 2013
TL;DR: This work proposes an on-chip network called SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) that aims to present a single-cycle data-path all the way from the source to the destination.
Abstract: As the number of on-chip cores increases, scalable on-chip topologies such as meshes inevitably add multiple hops in each network traversal. The best we can do right now is to design 1-cycle routers, such that the low-load network latency between a source and destination is equal to the number of routers + links (i.e. hops×2) between them. OS/compiler and cache coherence protocols designers often try to limit communication to within a few hops, since on-chip latency is critical for their scalability. In this work, we propose an on-chip network called SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) that aims to present a single-cycle data-path all the way from the source to the destination. We do not add any additional fast physical express links in the data-path; instead we drive the shared crossbars and links asynchronously up to multiple-hops within a single cycle. We design a router + link microarchitecture to achieve such a traversal, and a flow-control technique to arbitrate and setup multi-hop paths within a cycle. A place-and-routed design at 45nm achieves 11 hops within a 1GHz cycle for paths without turns (9 for paths with turns). We observe 5-8X reduction in low-load latencies across synthetic traffic patterns on an 8×8 CMP, compared to a baseline 1-cycle router. Full-system simulations with SPLASH-2 and PAR-SEC benchmarks demonstrate 27/52% and 20/59% reduction in runtime and EDP for Private/Shared L2 designs.

117 citations

Patent
14 Feb 2001
TL;DR: In this paper, a broadband communication system with improved latency is described, which employs distributed caching techniques to assemble data objects at locations proximate to a source to avoid latency over delayed links.
Abstract: A broadband communication system with improved latency is disclosed. The system employs distributed caching techniques to assemble data objects at locations proximate to a source to avoid latency over delayed links. The assembled data objects are then multicast to one or more remote terminals in response to a request for the objects, thus reducing unnecessary data flow across the satellite link.

117 citations

Patent
Gregory R. Roelofs1
22 Mar 2002
TL;DR: In this paper, the authors proposed a method of compensating for high-latency computer clients in a multi-player electronic game played on a plurality of terminals connected by a network.
Abstract: A method of compensating for high-latency computer clients in a multi-player electronic game played on a plurality of terminals connected by a network. The method includes: (a) determining a latency value for a plurality of computer clients operating said plurality of terminals; (b) determining a latency compensation factor from said determined latency value for each of said plurality of computer clients; and (c) adjusting a playing modality for at least one of said plurality of computer clients responsive to said determined latency compensation factor.

117 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
2021485
2020529
2019533
2018500
2017405