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Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.


Papers
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Journal ArticleDOI
TL;DR: Results showed a significant latency increase for the N1, P2, and P3 components in the processing disordered group, and the interpeak latency interval P2-P3 was significantly longer in the clinical group.
Abstract: The purpose of this study was to evaluate auditory event-related potentials, and related long latency components, in children with auditory processing disorders, and to compare these results with a normal group matched for age, intelligence, and gender. Results showed a significant latency increase for the N1, P2, and P3 components in the processing disordered group. Furthermore, the interpeak latency interval P2-P3 was significantly longer in the clinical group. In terms of amplitude measures, only P3 amplitude differed significantly between groups. These results suggest that the long latency potentials may be useful in the assessment of children with processing disorders.

110 citations

Patent
Jahagirdar Sanjeev1
11 Dec 2006
TL;DR: In this article, a system and a method for optimizing the latency of dynamic memory sizing is described, where the operating requirements can reflect the amount of memory required to perform commensurate operations.
Abstract: Some embodiments of the invention include a system and method for optimizing the latency of dynamic memory sizing. In some embodiments, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The latency of changes to the memory based on operating requirements is optimized by the method and system. Other embodiments are described.

110 citations

Patent
24 Jun 2003
TL;DR: In this article, a bypass or pass-through device is used to connect two HyperTransport links together where each of the links is connected to a processor at the other end.
Abstract: A technique and mechanism for reducing memory latency asymmetry in a multiprocessor system by replacing one (or more) processors with a bypass or pass-through device. Using the pass-through mechanism, the reduced number of processors in the system enables all of the remaining processors to connect to each other directly using the interconnect links. The reduction in processor count improves symmetry and reduces overall latency thereby potentially improving performance of certain applications despite having fewer processors. In one specific implementation, the pass through device is used to connect two HyperTransport links together where each of the links is connected to a processor at the other end.

110 citations

Patent
Ralph B. Case1, Brad B. Topol1
07 Jun 1999
TL;DR: In this paper, the authors define a technique for gathering latency information, which can be used in a variety of ways (such as making policy decisions that may limit the amount of data sent over a communications path due to detection of high latency in the network).
Abstract: A method, system, and computer-readable code for measuring network latency between a client computer and a server machine without requiring any additional software on the client. Network latency is a measurement that reflects the network round trip delay between a client machine and a server machine. The present invention defines a novel technique for gathering latency information. This information may be used in a variety of ways (such as making policy decisions that may limit the amount of data sent over a communications path due to detection of high latency in the network).

110 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20222
2021485
2020529
2019533
2018500
2017405