Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 7278 publications have been published within this topic receiving 115409 citations. The topic is also known as: lag.

Computation Hierarchy for In-network processing

Abstract: Explored the latency and energy tradeoffs introduced by the heterogeneity of sensor nodes in the netework.

Measurement and Application of Fault Latency

Abstract: The time interval between the occurrence of a fault and the detection of the error caused by the fault is divided by the generation of that error into two parts: fault latency and error latency. Since the moment of error generation is not directly observable, all related works in the literature have dealt with only the sum of fault and error latencies, thereby making the analysis of their separate effects impossible. To remedy this deficiency, we 1) present a new methodology for indirectly measuring fault latency, 2) derive the distribution of fault latency from the methodology, and 3) apply the knowledge of fault latency to the analysis of two important examples.

Energy Efficiency and Delay in 5G Ultra-Reliable Low-Latency Communications System Architectures

Abstract: Emerging 5G URLLC wireless systems are characterized by minimal over-the-air latency and stringent decoding error requirements. The low latency requirements can cause conflicts with 5G EE design targets. Therefore, this work provides a perspective on various trade-offs between energy efficiency and user plane delay for upcoming URLLC systems. For network infrastructure EE, we propose solutions that optimize base station on-off switching and distributed access network architectures. For URLLC devices, we advocate solutions that optimize EE of discontinuous reception (DRX), mobility measurements, and the handover process, respectively, without compromising on delay.

Towards low-latency and ultra-reliable vehicle-to-vehicle communication

Abstract: Recently vehicle-to-vehicle (V2V) communication emerged as a key enabling technology to ensure traffic safety and other mission-critical applications. In this paper, a novel proximity and quality-of-service (QoS)-aware resource allocation for V2V communication is proposed. The proposed approach exploits the spatial-temporal aspects of vehicles in terms of their physical proximity and traffic demands, to minimize the total transmission power while considering queuing latency and reliability. Due to the overhead caused by frequent information exchange between vehicles and the roadside unit (RSU), the centralized problem is decoupled into two interrelated subproblems. First, a novel RSU-assisted virtual clustering mechanism is proposed to group vehicles in zones based on their physical proximity. Given the vehicles' traffic demands and their QoS requirements, resource blocks are assigned to each zone. Second, leveraging techniques from Lyapunov stochastic optimization, a power minimization solution is proposed for each V2V pair within each zone. Simulation results for a Manhattan model have shown that the proposed scheme outperforms the baseline in terms of average queuing latency reduction up to 97% and significant improvement in reliability.

Method and apparatus for multiple latency synchronous pipelined dynamic random access memory

Abstract: A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through an input latch circuit by a feedback reset signal, such that commands are pipelined for three latency operation. In response to the command signals, the two latency control circuit produces a set of control signals according to a two latency algorithm. In response to the same command signals, the three latency control circuit independently produces a set of three latency control signals according to a three latency algorithm. In two latency operation, access time for signal development is externally controlled, while in three latency operation access time is internally controlled. In three latency operation, signal development time is determined separately for reads and writes. Also, in three latency operation, data is clocked along a data input path with a write latency. The multiple latency synchronous dynamic random access memory includes a pair of output data paths having different delays, where the data path is selected according to two or three latency operation.