Showing papers on "Latency (engineering) published in 1989"
TL;DR: Transmission conditional-sum (TGCS) adders realized in a standard 2.5- mu m CMOS technology are discussed and design and layout techniques are described in detail and experimental data is given.
Abstract: Transmission conditional-sum (TGCS) adders realized in a standard 2.5- mu m CMOS technology are discussed. These adders offer short propagation delay and latency time (12.5 ns for 32-b addition) and consume only moderate chip area (i.e. 80*460 mu m/sup 2/ for 1 b in a 32-b adder). They allow static operation and consume only dynamic power (like standard CMOS). The layout exhibits high regularity and can be easily adjusted to various word lengths. Design and layout techniques are described in detail and experimental data are given. >
25 citations
01 Mar 1989
TL;DR: In this article, an engineering design for a low latency high bandwidth interconnection network which will form the switching substrate for a multi-model parallel processing system is presented, which is enhanced with a variety of approaches covering interconnection protocols, routing, fault tolerance, advanced packaging, and electrical interconnection techniques.
Abstract: This paper presents an engineering design for a low latency high bandwidth interconnection network which will form the switching substrate for a multi-model parallel processing system. The performance is enhanced with a variety of approaches covering interconnection protocols, routing, fault tolerance, advanced packaging, and electrical interconnection techniques. The synergistic application of these technologies leads to a high performance design.
20 citations
01 Apr 1989
TL;DR: To compare the merits of these approaches, algorithms frequently encountered in numerical and symbolic computation were hand-coded for each architecture.
Abstract: The Scheme86 and the HP Precision Architectures represent different trends in computer processor design. The former uses wide micro-instructions, parallel hardware, and a low latency memory interface. The latter encourages pipelined implementation and visible interlocks. To compare the merits of these approaches, algorithms frequently encountered in numerical and symbolic computation were hand-coded for each architecture. Timings were done in simulators and the results were evaluated to determine the speed of each design. Based on these measurements, conclusions were drawn as to which aspects of each architecture are suitable for a high- performance computer.
1 citations