Showing papers on "Latency (engineering) published in 1993"

A Status Report on Research in Transparent Informed Prefetching (CMU-CS-93-113)

Abstract: This paper focuses on extending the power of caching and prefetching to reduce file read latencies by exploiting application level hints about future I/O accesses. We argue that systems that disclose high-level knowledge can transfer optimization information across module boundaries in a manner consistent with sound software engineering principles. Such Transparent Informed Prefetching (TIP) systems provide a technique for converting the high throughput of new technologies such as disk arrays and log-structured file systems into low latency for applications. Our preliminary experiments show that even without a high-throughput I/O subsystem TIP yields reduced execution time of up to 30% for applications obtaining data from a remote file server and up to 13% for applications obtaining data from a single local disk. These experiments indicate that greater performance benefits will be available when TIP is integrated with low level resource management policies and highly parallel I/O subsystems such as disk arrays.

Stari: a technique for high-bandwidth communication

Abstract: This dissertation presents a novel technique for high-bandwidth communication called STARI, Self-Timed At Receiver's Input. STARI is a hybrid of synchronous and self-timed design techniques. STARI is provably correct, well suited for CMOS implementation, and offers a practical, cost effective approach to interprocessor communication in a multiprocessor. To demonstrate STARI, a CMOS chip has been implemented and is described here. STARI is motivated by limitations of purely synchronous or purely self-timed hardware. This dissertation begins with an asymptotic analysis of the performance of self-timed pipelines. It is shown that self-timed pipelines can achieve linear speedup under an assumption of uniform interconnect delays. However, practical designs have non-uniform interconnect because of the hierarchy of packaging. In these designs, the performance is limited by the latency of the slowest interconnect. To exploit the high-bandwidth offered by STARI in a multiprocessor, each processor node must have a memory system that offers high-bandwidth data transfers to the STARI interface and low latency access to the local CPU. Dual-port memories allow both of these goals to be met. Consistency problems that arise when using dual-port memories are identified and two software solutions are presented and analyzed.

NPCPL : Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs

Abstract: High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both of t h e m simultaneously. We propose a Normal Process Complementary Pass Transistor Logic (NPCPL) which can be used as a universal logic to provide finest grain pipelining without affecting overall latency o r increasing the area. It does n o t require any special process steps and hence, can be Tealised in a normal process technology as against the CPL proposed by Yano et al [2] which uses threshold voltage adjustment of selected devices. The design procedure is described for (a)low latency, (b)high throughput and (c)low area requirements. In addition to the various advantages, it is envisioned that NPCPL designs can also be used to build ultra-high speed pipelined system without pipelining latches, viz., wave pipelined digital systems, where the throughput achievable is beyond that permitted by the delay of a pipeline stage.

Image tracking in real-time: a transputer emulation of some early mammalian vision processes

Abstract: By emulating some of the ‘early’ vision processes believed to occur in the visual cortex of mammals, dramatic savings can be made in the computational efforts usually associated with image processing. This paper describes the design and implementation of a low-cost visual tracking system that uses no special signal processing, vector processing nor floatingpoint hardware. Its effectiveness relies only on the parallel replication of fast sealer integer processors with low latency communications. The current implementation uses 10 T425 transputers, processes 544 × 544 byte-pixel images at camera frame rates and provides 100 Hz. tracking feedback signals to the camera pan-and-tilt motors with a latency of no more than one-fifth of a second. The system will track any object that occupies the (majority of the) centre of the field of view moving against any background — no special lighting conditions or artificial scenery are required. The design and implementation follow naturally parallel structures and are expressed at all levels in occam.

High-speed low-latency portable visual-sensing system

Abstract: My work in the field of computer vision has focused on building high speed visual tracking systems to provide position feedback for the control of unstable tasks. In order to make a juggling robot or a robotic helicopter stable, three qualities are essential -- high update rate, low latency, and decent accuracy and resolution. We want to put multiple vision systems on small robotic devices with limited payloads. Therefore the system must be very small, light, and cheap. However, we allow marking of the environment so the sophistication of the vision task can be extremely low. These constraints guided the development of AVS (which, due to lack of a better name, stands for Anne's Vision System).© (1993) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Low latency architectures for wave digital filters

Abstract: Wave digital filters constructed of networks of two port adaptors are candidates for VLSI implementation. Pipelining, and hence high data throughput, requires a low latency, high throughput, hardware structure for the two-port adaptor. This design problem is addressed in two main approaches, i.e., with systolic array techniques based on lsb first pipelining that exploit the low coefficient wordlength properties of wave digital filters, and with msb first pipelining based on signed digit number systems. These methods are extended, compared and contrasted; a new hardware scheme is presented; and it is indicated which arrangements are best suited for particular filtering applications. >

Using a private SMDS/ATM network to provide long-haul supercomputing visualization services

Abstract: Sandia National Laboratories is prototyping a service for providing a distributed visualization capability between its Albuquerque, New Mexico and Livermore, California sites. The service will allow TCP/EP LAN users to process computationally intensive codes on the Cray Y-MP 8/864 and use the Application Visualization System, (AVS) running on a visualization server to display the results to desktops in Livermore (or Albuquerque). The long-haul environment presents several technical challenges such as high delays (up to 42 milliseconds), potential error rates, and security concerns which can affect the quality of the services. The network design requires low latency switch gear and high speed LAN connections (FDDI) to make the visualization/computational services useful to the customer. This paper will describe tie network design used and will report performance characteristics of the applications utilizing this service.

Interconnection structures for highly parallel systems

Abstract: The interconnection network design space and directions of its potential evolution are discussed. Communications within highly-parallel systems can be classified in two categories: input/output (I/O)-related communications which involve the transfer of large blocks of data and take place across the memory hierarchy of the system; and communications which typically involve the transfer of small units of information needed for process execution. These two types of communication have distinctly different transfer characteristics, the former requiring primarily high-throughput while the latter very low latency. As the capabilities of processors increase, the system communication requirements become more stringent. The author examines interconnection network structures and trends in underlying network implementation technologies that are needed to meet this challenge. >

Modelling ATM switch-fabric based on the knockout principle

Abstract: Within high speed integrated communications networks, the user expects data to arrive 'as is' in a delay- and error-free manner. Switching fabrics put in place to support the realisation of B-ISDN applications within these networks must have short latencies, and be capable of delivering cells from source to destination in order and without loss. The knockout switch, an N-input x N-output switch, has the characteristics of: being non-blocking (i.e. every incoming cell has access to every output port), low latency, self routing, complete sharing of buffer memory, ensuring all cells are treated in a first-in-first out basis, and its architecture allows for modular growth. Its fully connected switch fabric ensures all incoming cells have a direct path to every output. Incoming cells are filtered to ensure that only those destined for a particular output port access that port. Each output requires N filters, therefore N/sup 2/ filters are needed for the entire switch. The authors show how to model an asynchronous transfer mode switch based on the knockout principle. The intended scenario will simulate the arrival of cells from a high speed network to a switch, their processing and final departure from an appropriate port. The switch will be based on an 8 input by 8 output port architecture.