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Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.


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Journal ArticleDOI
07 May 2020
TL;DR: This work performs an extensive investigation and constructs a portfolio of S-boxes suitable for secure lightweight implementations, which aligns well with the ongoing NIST Lightweight Cryptography competition and targets good functional properties and efficient implementations in terms of AND depth and AND gate complexity.
Abstract: In this work, we perform an extensive investigation and construct a portfolio of S-boxes suitable for secure lightweight implementations, which aligns well with the ongoing NIST Lightweight Cryptography competition. In particular, we target good functional properties on the one hand and efficient implementations in terms of AND depth and AND gate complexity on the other. Moreover, we also consider the implementation of the inverse S-box and the possibility for it to share resources with the forward S-box. We take our exploration beyond the conventional small (and even) S-box sizes. Our investigation is twofold: (1) we note that implementations of existing S-boxes are not optimized for the criteria which define masking complexity (AND depth and AND gate complexity) and improve a tool published at FSE 2016 by Stoffelen in order to fill this gap. (2) We search for new S-box designs which take these implementation properties into account from the start. We perform a systematic search based on the properties of not only the S-box but also its inverse as well as an exploration of larger S-box sizes using length-doubling structures. The result of our investigation is not only a wide selection of very good S-boxes, but we also provide complete descriptions of their circuits, enabling their integration into future work.

22 citations

Journal ArticleDOI
TL;DR: A method for an automated synthesis of low-latency asynchronous controllers is presented and a software tool called OptiMist, which successfully interfaces conventional EDA design flow for simulation, timing analysis, and place-and-route, is developed.
Abstract: A method for an automated synthesis of low-latency asynchronous controllers is presented It is based on a direct mapping approach and starts from an initial specification in the form of a signal transition graph (STG) This STG is split into a device and an environment, which synchronize via a communication net that models wires The device is represented as a tracker and a bouncer The tracker follows the state of the environment and provides reference points to the device outputs The bouncer communicates with the environment and generates output events in response to the input events according to the state of the tracker This two-level architecture provides an efficient interface to the environment and is convenient for subsequent mapping into a circuit netlist A set of optimization heuristics is developed to reduce the latency and size of the circuit As a result of this paper, a software tool called OptiMist has been developed Its low algorithmic complexity allows large specifications to be synthesized, which is not possible for the tools based on state-space exploration OptiMist successfully interfaces conventional EDA design flow for simulation, timing analysis, and place-and-route

21 citations

Journal ArticleDOI
TL;DR: This work introduces a special elastic optical network paradigm called the ultradense wavelength switched network (UD-WSN) for metro optical networks, which supports a spectrum granularity finer than the current smallest standardized 12.5 GHz, which enables more efficient spectrum utilization when provisioning metro lowspeed service connections.
Abstract: Intensive video and cloud computing services are putting much pressure on metro networks to meet stringent requirements such as low latency, low power consumption, and high spectral efficiency, where the system cost is sensitive To address this challenge, we introduce a special elastic optical network paradigm called the ultradense wavelength switched network (UD-WSN) for metro optical networks The architecture supports a spectrum granularity (eg, 625 GHz or even 5 GHz) finer than the current smallest standardized 125 GHz, which enables more efficient spectrum utilization when provisioning metro lowspeed service connections (eg, sub-1G/1G/10G services) The performance of UD-WSN is evaluated from the techno-economic perspective in comparison with the conventional OTN over DWDM network Case studies demonstrate the merits of the proposed architecture Considering the promising potential of UD-WSN, we also suggest several open research issues for it

21 citations

Journal ArticleDOI
TL;DR: The evaluation results on up to 55,296 nodes of the K computer show the new implementation of MPI collective communication outperforms the existing one for long messages by a factor of 4 to 11 times and shows the short-message algorithms complement the long-message ones.
Abstract: This paper proposes the design of ultra scalable MPI collective communication for the K computer, which consists of 82,944 computing nodes and is the world's first system over 10 PFLOPS. The nodes are connected by a Tofu interconnect that introduces six dimensional mesh/torus topology. Existing MPI libraries, however, perform poorly on such a direct network system since they assume typical cluster environments. Thus, we design collective algorithms optimized for the K computer. On the design of the algorithms, we place importance on collision-freeness for long messages and low latency for short messages. The long-message algorithms use multiple RDMA network interfaces and consist of neighbor communication in order to gain high bandwidth and avoid message collisions. On the other hand, the short-message algorithms are designed to reduce software overhead, which comes from the number of relaying nodes. The evaluation results on up to 55,296 nodes of the K computer show the new implementation outperforms the existing one for long messages by a factor of 4 to 11 times. It also shows the short-message algorithms complement the long-message ones.

21 citations

Proceedings ArticleDOI
23 Oct 2006
TL;DR: The measured performances in the prototype with the proposed parallel architecture, including inter-DSP data communication performance and system computing capacity, show high data transfer bandwidth with low latency as well as high image processing performance, which achieve a good balance for parallel image processing.
Abstract: A DSP/FPGA-based parallel architecture oriented to real-time image processing applications is presented. The architecture is structured with high performance DSPs interconnected by FPGA. Within FPGA a FIFO interconnection network and the specific data communication protocol are implemented, which interconnect 3 DSPs (TMS320C6414) effectively. The measured performances in the prototype with the proposed parallel architecture, including inter-DSP data communication performance and system computing capacity, show high data transfer bandwidth (up to 400 Mbytes/s) with low latency as well as high image processing performance, which achieve a good balance for parallel image processing.

21 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202210
2021692
2020481
2019389
2018366
2017227