Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.

EDGE: A Routing Algorithm for Maximizing Throughput and Minimizing Delay in Wireless Sensor Networks

Abstract: Wireless sensor networks are distributed event-based systems with severe energy constraints, variable quality links, low data-rate and many-to-one event-to-sink flows. Communication algorithms for sensor networks, such as directed diffusion, are designed to operate efficiently under these constraints. However, directed diffusion is not efficient in more challenging domains, such as video sensor networks, because of the high throughput and low delay requirements of multimedia data. Instead, we propose EDGE - a greedy algorithm based on directed diffusion that reinforces routes with high link quality and low latency, thus maximizing throughput and minimizing delay. ETX (Expected Transmission Count) is used as the metric for measuring link quality. This paper presents an improved method for computing aggregate ETX for a path that increases end-to-end throughput. Simulation results with CBR (constant bit rate) traffic show that our proposed distributed algorithm selects routes that give better throughput than those reinforced by standard directed diffusion, while maintaining low delay.

FISCO: A Fully Integrated Scheme of Self-Configuration and Self-Organization for WSN

Abstract: To enable spontaneous communications in wireless sensors networks, both self-configuration and self-organization appear to be two fundamental mechanisms. However, the majority of prior contributions in ad hoc network suffer from the low processing capability, limited storage space, energy constraint and large number of nodes when being applied in wireless sensor networks. Moreover, self-configuration and self-organization have been always considered as two independent mechanisms. The authors believe that this consideration leads to inefficient network and redundant protocol cost. Hence, in this paper a fully integrated scheme of self-configuration and self-organization was proposed. It can better resolve the distributed address allocation using the structure generated by itself with low message overhead. It also provides significant energy savings comparing to other schemes and low latency.

Distributed Join-the-Idle-Queue for Low Latency Cloud Services

Abstract: Low latency is highly desirable for cloud services. To achieve a low response time, stringent timing requirements are needed for task scheduling in a large-scale server farm spanning thousands of servers. In this paper, we conduct an in-depth analysis for distributed Join-the-Idle-Queue (JIQ), a promising new approximation of an idealized task-scheduling algorithm. In particular, we derive semi-closed form expressions for the delay performance of distributed JIQ, and we propose a new variant of distributed JIQ that offers clear advantages over alternative algorithms for large systems.

A Low-Latency FPGA Implementation for Real-Time Object Detection

Abstract: The advancement of object detection algorithms makes them widely used in autonomous systems. However, due to high computational complexity of Convolutional Neural Networks(CNN), stringent latency requirement is hard to meet for real-time object detection. To address this problem, a low-latency accelerator architecture is proposed in this paper. A finegrained column-based pipeline architecture with padding skip technique is implemented to reduce the start-up time of pipeline. In order to cut down the computational time of CNN, double signed-multiplication correcting circuit is introduced. In addition, pooling unit with share buffer is proposed to reduce storage cost for pooling layer. To demonstrate our new architecture, we implement the YOLOv2-tiny deep neural network (you-only-look-once) with input size 1280×384 on ZC706 development board, improving the latency by 2.125× to 2.34× compared to previous FPGA accelerator for YOLOv2-tiny.

A Passive Solution to the CPU Resource Discovery Problem in Cluster Grid Networks

Abstract: We present the details of a novel method for passive resource discovery in cluster grid environments, where resources constantly utilize internode communication. Our method offers the ability to nonintrusively identify resources that have available CPU cycles; this is critical for lowering queue wait times in large cluster grid networks. The benefits include: 1) low message complexity, which facilitates low latency in distributed networks, 2) scalability, which provides support for very large networks, and 3) low maintainability, since no additional software is needed on compute resources. Using a 50-node (multicore) test bed (DETERlab), we demonstrate the feasibility of our method with experiments utilizing TCP, UDP, and ICMP network traffic. We use a simple but powerful technique that monitors the frequency of network packets emitted from the Network Interface Card (NIC) of local resources. We observed the correlation between CPU load and the timely response of network traffic. A highly utilized CPU will have numerous, active processes which require context switching. The latency associated with numerous context switches manifests as a delay signature within the packet transmission process. Our method detects that delay signature to determine the utilization of network resources. Results show that our method can consistently and accurately identify nodes with available CPU cycles (<;70 percent CPU utilization) through analysis of existing network traffic, including network traffic that has passed through a switch (noncongested). Also, in situations where there is no existing network traffic for nodes, ICMP ping replies can be used to ascertain this resource information.