Latency (engineering)

About: Latency (engineering) is a research topic. Over the lifetime, 3729 publications have been published within this topic receiving 39210 citations. The topic is also known as: lag.

An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems

Abstract: Deeply pipelined systems require flip-flops with low latency and power consumption. Often, the flip-flop must supply both inverted and non-inverted signals to subsequent logic. Generating both outputs at the same time improves performance by equalizing the worst-case delays. In this paper, we present a novel differential flip-flop for deeply pipelined systems. The circuit uses cross-coupled p-transistors as pull-up devices to achieve high energy efficiency. We simulated the design in 90-nm CMOS technology to determine the delay and power consumption. We then repeated the analysis with four other differential flip-flops that produce symmetric outputs. The proposed design achieves the best power-delay product of the five alternatives.

CMOS implementation of a fast 4-2 compressor for parallel accumulations

Abstract: This paper discusses about the design of a novel and fast 4-2 compressor. To enhance the speed performance, some changes are performed in the truth table of conventional 4-2 compressor which leaded to reduction of gate level delay to 2 XOR logic gates plus 1 transistor for all parameters. Because of similar paths, there will be no need for extra buffers in low latency paths to equalize the delays. Therefore, the power dissipation will be decreased and the output waveforms will be free of any glitch. The delay of proposed architecture is 340ps which is simulated by HSPICE using TSMC 0.35µm CMOS technology.

Dynamically adjusting frame mtu to support low-latency communication

Abstract: In one embodiment, a sender in a shared-communication network determines whether a pending frame is low-latency or high-throughput, and sets a maximum transmission unit (MTU) of the pending frame as a first MTU in response to a low- latency frame and a longer second MTU in response to a high-throughput frame. In another embodiment, a receiver receives a data frame from a sender according to an MTU, and determines a trigger for adjusting the MTU based on latency requirements. In response to the trigger, the receiver sets an interrupt flag in a link-layer acknowledgment for the received data frame. In still another embodiment, a sender determines a pending low-latency data frame to send to a receiver operating according to an MTU, and sends a control message to the receiver to indicate the pending low- latency data frame and an adjusted MTU.

On All-to-All Broadcast in Dense Gaussian Network On-Chip

Abstract: Gaussian networks are gaining popularity as good candidates Network On-Chip (NoC) for interconnecting Multiprocessor System-on-Chips (MPSoCs). They showed better topological properties compared to the 2D torus networks with the same number of nodes $N$ and the same degree 4. All-to-all broadcast is a collective communication algorithm used frequently in many parallel applications. Recently, Z. Zhang et al. [1] have proposed an all-to-all broadcast algorithm for Gaussian on-chip networks that achieves the minimum delay time but requires 4 $k$ extra buffers per router, where $k$ is the network diameter. In this paper, we propose a new all-to-all broadcast algorithm for dense Gaussian on-chip networks that achieves the minimum delay time without requiring any extra buffers per router. In this paper, we propose a new all-to-all broadcast algorithm for dense Gaussian on-chip networks that achieves the minimum delay time without requiring any extra buffers per router. Along with low latency, reducing the amount of buffer space and power consumption are very important issues in NoCs architectures.

Randomly Optimized Grid Graph for Low-Latency Interconnection Networks

Abstract: In this work we present randomly optimized grid graphs that maximize the performance measure, such as diameter and average shortest path length (ASPL), with subject to limited edge length on a grid surface. We also provide theoretical lower bounds of the diameter and the ASPL, which prove optimality of our randomly optimized grid graphs. We further present a diagonal grid layout that significantly reduces the diameter compared to the conventional one under the edge-length limitation. We finally show their applications to three case studies of off-and on-chip interconnection networks. Our design efficiently improves their performance measures, such as end-to-end communication latency, network power consumption, cost, and execution time of parallel benchmarks.